|
TC1130_08 Datasheet, PDF (71/114 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller | |||
|
◁ |
TC1130
Functional Description
3.23
On-Chip Debug Support
The On-Chip Debug Support of the TC1130 consists of the following building blocks:
⢠OCDS L1 module of TriCoreâ¢
⢠OCDS L2 interface of TriCoreâ¢
⢠OCDS L1 module in the BCU of the FPI Bus
⢠OCDS L1 facilities within the DMA
⢠OCDS L2 interface of DMA
⢠OCDS System Control Unit (OSCU)
⢠Multi Core Break Switch (MCBS)
⢠JTAG based Debug Interface (Cerberus JDI)
⢠Suspend functionality of peripherals
Features:
⢠TriCore⢠L1 OCDS:
â Hardware event generation unit
â Break by DEBUG instruction or break signal
â Full Single-Step support in hardware, possible also with software break
â Access to memory, SFRs, etc. on the fly
⢠DMA L1 OCDS:
â Output break request on errors
â Suspension of pre-selected channels
⢠Level 2 trace port with 16 pins that outputs either TriCoreâ¢, or DMA trace
⢠OCDS System Control Unit (Cerberus OSCU)
â Minimum number of pins required (no OCDS enable pin)
â Hardware allows hot attach of a debugger to a running system
â System is secure (can be locked from internal)
⢠Multi Core Break Switch (Cerberus MCBS):
â TriCoreâ¢, DMA, break pins, and BCUs as break sources
â TriCore⢠as break targets; other parts can in addition be suspended
â Synchronous stop and restart of the system
â Break to Suspend converter
Figure 3-15 shows a basic block diagram of the building blocks.
Data Sheet
65
V1.1, 2008-12
|
▷ |