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TC1130_08 Datasheet, PDF (7/114 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller | |||
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32-Bit Single-Chip Microcontroller
TriCore⢠Family
TC1130
1
Summary of Features
⢠High Performance 32-bit TriCore⢠V1.3 CPU with 4-Stage Pipeline
⢠Floating Point Unit (FPU)
⢠Dual Issue super-scalar implementation
â MAC Instruction maximum triple issue
⢠Circular Buffer and bit-reverse addressing modes for DSP algorithms
⢠Very fast interrupt response time
⢠Hardware controlled context switch for task switch and interrupts
⢠Memory Management Unit (MMU)
⢠On-chip Memory
â 28-Kbyte Data Memory (SPRAM)
â 32-Kbyte Code Memory (SPRAM)
â 16-Kbyte Instruction Cache (ICACHE)
â 4-Kbyte Data Cache (DCACHE)
â 64-Kbyte SRAM Data Memory Unit (DMU)
â 16-Kbyte Boot ROM
⢠On-chip Bus Systems
â 64-bit High Performance Local Memory Bus (LMB) for fast access between caches
and on-local memories and FPI Interface
â On-chip Flexible Peripheral Interconnect Bus (FPI) for interconnections of
functional units
⢠DMA Controller with 8 channels for data transfer operations between peripheral units
and memory locations
⢠Two high speed Micro Link Interfaces (MLI0/1) for controller communication and
emulation
⢠Flexible External Bus Interface Unit (EBU) to access external data memories
⢠One Multifunctional General Purpose Timer Unit (GPTU) with three 32-bit timer/
counters
⢠Two Capture and Compare units (CCU60/1) for PWM signal generation, each with
â 3-channel, 16 bit Capture and Compare unit
â 1-channel, 16 bit Compare unit
⢠Three Asynchronous/Synchronous Serial Channels (ASC0/1/2) with baud-rate
generator, parity, framing and overrun error detection, support FIFO and IrDA data
transmission
⢠Two High Speed Synchronous Serial Channels (SSC0/1) with programmable data
length, FIFO support and shift direction
Data Sheet
1
V1.1, 2008-12
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