TC1130_08 Datasheet, PDF (35/114 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller

TC1130
Functional Description
3.4
On-Chip Bus System
The TC1130 includes two bus systems:
• Local Memory Bus (LMB)
• Flexible Peripheral Interface Bus (FPI)
The LMB-to-FPI (LFI) bridge interconnects the FPI bus and LMB Bus.
3.4.1 Local Memory Bus (LMB)
The Local Memory Bus interconnects the memory units and functional units, such as
CPU and DMU. The main objective of the LMB bus is to support devices with fast
response time. This allows the DMI and PMI fast access to local memory and reduces
load on the FPI bus. The TriCore™ system itself is located on the LMB bus. Via External
Bus Unit, it interconnects TC1130 and external components.
The Local Memory Bus is a synchronous, pipelined, split bus with variable block size
transfer support. It supports 8, 16, 32 and 64 bits single beat transactions and variable
length 64 bits block transfers.
Features:
The LMB provides the following features:
• Synchronous, Pipelined, Multimaster, 64-bit high performance bus
• Optimized for high speed and high performance
• 32-bit address, 64-bit data buses
• Central, simple per cycle arbitration
• Slave controlled wait state insertion
• Address pipelining (max depth - 2)
• Supports Split transactions
• Supports Variable block size transfer
• Supports Locked transaction (read-modify-write)
3.4.2 Flexible Peripheral Interconnect Bus (FPI)
The FPI Bus is an on-chip bus that is used in modular and highly integrated
microprocessors and microcontrollers (systems-on-chips). FPI Bus is designed for
memory mapped data transfers between its bus agents. Bus agents are on-chip function
blocks (modules), equipped with an FPI Bus interface and connected via FPI Bus
signals. An FPI Bus agent acts as an FPI Bus master when it initiates data read or data
write operations once bus ownership has been granted to the agent. An FPI Bus agent
that is addressed by an FPI Bus operation acts as an FPI Bus slave when it performs the
requested data read or write operation.
Data Sheet
29
V1.1, 2008-12