TC1130_08 Datasheet, PDF (63/114 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller

TC1130
Functional Description
RB and TB provide on-chip data buffering whereas DMUR and DMUT perform data
transfer from/to the shared memory.
Two interfaces are provided by the Ethernet Controller module:
• MII interface for connection of Ethernet PHYs via 18 Input/Output lines
• Master/slave FPI bus interface for connection to the on-chip system bus for data
transfer as well as configuration
Features:
• Media Independent Interface (MII) according to IEEE 802.3
• Supports 10 or 100 Mbit/sec MII-based Physical devices
• Supports Full Duplex Ethernet
• Supports data transfer between Ethernet Controller and COM-DRAM
• Supports data transfer between Ethernet Controller and SDRAM via EBU
• 256 x 32 bit Receive buffer and Transmit buffer each
• Supports burst transfers up to 8 x 32 Bytes
Media Access Controller (MAC)
• 100/10 Mbit/sec operations
• Full IEEE 802.3 compliance
• Station management signaling
• Large on-chip CAM (Content Addressable Memory)
• Full duplex mode
• 80-byte transmit FIFO
• 16-byte receive FIFO
• PAUSE Operation
• Flexible MAC Control Support
• Supports Long Packet mode and Short Packet mode
• PAD generation
Media Independent Interface (MII)
• Media independence
• Multi-vendor point of interoperability
• Supports connection of MAC layer and Physical (PHY) layer devices
• Capable of supporting both 100 Mbit/sec and 10 Mbit/sec data rates
• Data and delimiters are synchronous to clock references
• Provides independent four bits wide transmit and receive data paths
• Supports connection of PHY layer and Station Management (STA) devices
• Provides a simple management interface
• Capable of driving a limited length of shielded cable
Data Sheet
57
V1.1, 2008-12