TC1130_08 Datasheet, PDF (49/114 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller

TC1130
Functional Description
3.11 Inter IC Serial Interface (IIC)
Figure 3-7 shows a global view of the functional blocks of the Inter IC Serial interface
(IIC).
The IIC module has four I/O lines, located at Port 2. The IIC module is further supplied
with clock control, interrupt control and address decoding logic. One DMA request can
be generated by IIC module.
Clock ^fIIC
Control
Address
Decoder
Interrupt
Control
INT_P
INT_E
INT_D
IIC
Module
SDA0
SCL0
SDA1
SCL1
Port 2
Control
P2.12/SDA0
P2.13/SCL0
P2.14/SDA1
P2.15/SCL1
to DMA
Figure 3-7 General Block Diagram of the IIC Interface
The on-chip IIC bus module connects the platform buses to other external controllers
and/or peripherals via the two-line serial IIC interface. One line is responsible for clock
transfer and synchronization (SCL), the other is responsible for the data transfer (SDA).
The IIC bus module provides communication at data rates of up to 400 kbit/sec and
features 7-bit addressing as well as 10-bit addressing. This module is fully compatible to
the IIC bus protocol.
The module can operate in three different modes:
Master mode, where the IIC controls the bus transactions and provides the clock signal.
Slave mode, where an external master controls the bus transactions and provides the
clock signal.
Multimaster mode, where several masters can be connected to the bus, i.e. the IIC can
be master or slave.
The on-chip IIC bus module allows efficient communication via the common IIC bus. The
module unloads the CPU of low level tasks such as:
• (De)Serialization of bus data
• Generation of start and stop conditions
• Monitoring the bus lines in slave mode
Data Sheet
43
V1.1, 2008-12