TC1130_08 Datasheet, PDF (48/114 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller

TC1130
Functional Description
Clock
Control
f_SSC0
f_CLC0
Address
Decoder
SSC0
Module
(Kernel)
EIR
Interrupt TIR
Control RIR
to DMA
Clock
Control
f_SSC1
f_CLC1
Address
Decoder
SSC1
Module
(Kernel)
EIR
Interrupt TIR
Control RIR
to DMA
M/S Select¹⁾
Enable¹⁾
Master
Slave
Slave
Master
MRSTA
MRSTB
MTSR
MTSRA
MTSRB
MRST
SCLKA
SCLKB
SLCK
M/S Select ¹⁾
Enable ¹⁾
Port 2
Control
Slave
SLSI1
SLSI[7:2] ¹⁾
Master
SLSO0
SLSO[2:1]
SLSO[4:3]
SLSO[7:5]
Port 1
Control
Port 0
Control
Slave
SLSI1
SLSI[7:2] ¹⁾
Master
SLSO0
SLSO[2:1]
SLSO[4:3]
SLSO[7:5]
Port 3
Control
Port 1
Control
Master
Slave
Slave
Master
MRSTA
MRSTB
MTSR
MTSRA
MTSRB
MRST
SCLKA
SCLKB
SLCK
Port 2
Control
1) _{These lines are not connected}
P2.2/MRST0
P2.3/MTSR0
P2.4/SCLK0
P2.12/SLSO03
P2.14/SLSO04
P1.15/SLSI0
P1.11/SLSO01
P1.13/SLSO02
P0.6/SLSO00
P0.4/SLSI1
P0.7/SLSO10
P3.7/SLSO05
P3.9/SLSO06
P3.11/SLSO07
P3.8/SLSO15
P3.10/SLSO16
P3.12/SLSO17
P1.12/SLSO11
P1.14/SLSO12
P2.13/SLSO13
P2.15/SLSO14
P2.5/MRST1A
P3.13/MRST1B
P2.6/MTSR1A
P3.14/MTSR1B
P2.7SCLK1A
P3.15/SCLK1B
MCB04486_mod
Figure 3-6 General Block Diagram of the SSC Interfaces
Data Sheet
42
V1.1, 2008-12