TC1130_08 Datasheet, PDF (56/114 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller

TC1130
Functional Description
3.14 Micro Link Serial Bus Interface (MLI)
Figure 3-10 shows a global view of the functional blocks of two Micro Link Serial Bus
interfaces (MLI0 and MLI1).
Clock
Control
f _MLI0
Address
Decoder
Interrupt
Control
DMA
INT_O
[3:0]
INT_O
[7:4]
MLI
Interface
MLI0
Module
(Kernel)
TCLK
TREADYA
TVALIDA
TDATA
RCLKA
RREADYA
RVALIDA
RDATAA
Port
0
Control
TCLK
TREADYB
TVALIDB
TDATA
RCLKB
RREADYB
RVALIDB
RDATAB
Port
4
Control
P0.8/
TCLK0A
P0.9/
TREADY0A
P0.10/
TVALID0A
P0.11/
TDATA0A
P0.12/RCLK0A
P0.13/
RREADY0A
P0.14/
RVALID0A
P0.15/
RDATA0A
P4.0/
TCLK0B
P4.1/
TREADY0B
P4.2/
TVALID0B
P4.3/
TDATA0B
P4.4/RCLK0B
P4.5/
RREADY0B
P4.6/
RVALID0B
P4.7/
RDATA0B
Clock
Control
f _MLI1
Address
Decoder
Interrupt
Control
DMA
INT_O
[1:0]
INT_O
[7:4]
MLI
Interface
MLI1
Module
(Kernel)
TCLK
TREADYA
TVALIDA
TDATA
RCLKA
RREADYA
RVALIDA
RDATAA
Port
3
Control
P3.8 /TCLK1
P3.9 /
TREADY1A
P3.10 /
TVALID1A
P3.11 /
TDATA1
P3.12/
RCLK1A
P3.13 /
RREADY1A
P3.14 /
RVALID1A
P3.15 /
RDATA1A
MLI_Interfaces
Figure 3-10 General Block Diagram of the MLI0 and MLI1 Interfaces
Data Sheet
50
V1.1, 2008-12