TLD5541-1QV Datasheet, PDF (61/82 Pages) Infineon Technologies AG – H-Bridge DC/DC Controller with SPI Interface

H-Bridge DC/DC Controller with SPI Interface
TLD5541-1QV
Serial Peripheral Interface (SPI)
device 1
device 2
device 3
SI
SO SI
SO SI
SO
MO
SPI
SPI
SPI
MI
MCSN
MCLK
SPI_DaisyChain_1.emf
Figure 12-3 Daisy Chain Configuration
In the SPI block of each device, there is one shift register where each bit from the SI line is shifted in with each
SCLK. The bit shifted out occurs at the SO pin. After sixteen SCLK cycles, the data transfer for one device is
finished. In single chip configuration, the CSN line must turn HIGH to make the device acknowledge the transferred
data. In daisy chain configuration, the data shifted out at device 1 has been shifted in to device 2. When using
three devices in daisy chain, several multiples of 8 bits have to be shifted through the devices (depending on how
many devices with 8 bit SPI and how many with 16 bit SPI). After that, the MCSN line must turn HIGH (see
Figure 12-4).
MI
MO
MCSN
MCLK
SO device 3
SI device 3
SO device 2
SI device 2
SO device 1
SI device 1
Figure 12-4 Data Transfer in Daisy Chain Configuration
SPI_DaisyChain_2.emf
Data Sheet
61
Rev. 1.0, 2016-05-20