TLD5541-1QV Datasheet, PDF (60/82 Pages) Infineon Technologies AG – H-Bridge DC/DC Controller with SPI Interface

H-Bridge DC/DC Controller with SPI Interface
TLD5541-1QV
Serial Peripheral Interface (SPI)
STDDIAG.TER
SI
OR
CSN
SCLK
S
SI SPI ^SO
S
1
SO
0
SPI_16bitTER .emf
Figure 12-2 Combinatorial Logic for TER bit
CSN LOW to HIGH Transition
• Command decoding is only done, when after the falling edge of CSN exactly a multiple (0,1, 2, 3, …) of eight
SCLK signals have been detected after the first 16 SCLK pulses. In case of faulty transmission, the
transmission error bit (TER) is set and the command is ignored.
• Data from shift register is transferred into the addressed register.
SCLK - Serial Clock
This input pin clocks the internal shift register. The serial input (SI) transfers data into the shift register on the falling
edge of SCLK while the serial output (SO) shifts diagnostic information out on the rising edge of the serial clock.
It is essential that the SCLK pin is in LOW state whenever chip select CSN makes any transition, otherwise the
command may be not accepted.
SI - Serial Input
Serial input data bits are shift-in at this pin, the most significant bit first. SI information is read on the falling edge
of SCLK. The input data consists of two parts, control bits followed by data bits. Please refer to Chapter 12.5 for
further information.
SO Serial Output
Data is shifted out serially at this pin, the most significant bit first. SO is in high impedance state until the CSN pin
goes to LOW state. New data will appear at the SO pin following the rising edge of SCLK.
Please refer to Chapter 12.5 for further information.
12.2
Daisy Chain Capability
The SPI of the TLD5541-1QV provides daisy chain capability. In this configuration several devices are activated
by the same CSN signal MCSN. The SI line of one device is connected with the SO line of another device (see
Figure 12-3), in order to build a chain. The end of the chain is connected to the output and input of the master
device, MO and MI respectively. The master device provides the master clock MCLK which is connected to the
SCLK line of each device in the chain.
Data Sheet
60
Rev. 1.0, 2016-05-20