XC164KM Datasheet, PDF (58/62 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core

XC164KM
Derivatives
Electrical Parameters
4.3.2 On-chip Flash Operation
The XC164KM’s Flash module delivers data within a fixed access time (see Table 4-7).
Accesses to the Flash module are controlled by the PMI and take 1+WS clock cycles,
where WS is the number of Flash access waitstates selected via bitfield WSFLASH in
register IMBCTRL. The resulting duration of the access phase must cover the access
time t_ACC of the Flash array. The required Flash waitstates depend on the actual system
frequency.
Note: The Flash access waitstates only affect non-sequential accesses. Due to
prefetching mechanisms, the performance for sequential accesses (depending on
the software structure) is only partially influenced by waitstates.
In typical applications, eliminating one waitstate increases the average
performance by 5% … 15%.
Table 4-7 Flash Characteristics (Operating Conditions apply)
Parameter
Symbol
Limit Values
Unit
Min. Typ. Max.
Flash module access time
t_ACC
Programming time per 128-byte block t_PR
Erase time per sector
t_ER
CC –
CC –
CC –
–
50¹⁾
ns
2²⁾
5
ms
200²⁾ 500
ms
1) The actual access time is influenced by the system frequency, see Table 4-8.
2) Programming and erase time depends on the system frequency. Typical values are valid for 40MHz.
Example: For an operating frequency of 40 MHz (clock cycle = 25 ns), the Flash
accesses must be executed with 1 waitstate: ((1+1) × 25 ns) ≥ 50 ns.
Table 4-8 indicates the interrelation of waitstates and system frequency.
Table 4-8 Flash Access Waitstates
Required Waitstates
Frequency Range
0 WS (WSFLASH = 00_B)
1 WS (WSFLASH = 01_B)
f_CPU ≤ 20 MHz
f_CPU ≤ 40 MHz
Note: The maximum achievable system frequency is limited by the properties of the
respective derivative, i.e. 40 MHz (or 20 MHz for XC164KM-xF20F devices).
Data Sheet
56
V1.0, 2005-11