XC164KM Datasheet, PDF (16/62 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core

XC164KM
Derivatives
Functional Description
3
Functional Description
The architecture of the XC164KM combines advantages of RISC, CISC, and DSP
processors with an advanced peripheral subsystem in a very well-balanced way. In
addition, the on-chip memory blocks allow the design of compact systems-on-silicon with
maximum performance (computing, control, communication).
The on-chip memory blocks (program code-memory and SRAM, dual-port RAM, data
SRAM) and the set of generic peripherals are connected to the CPU via separate buses.
Another bus, the LXBus, connects additional on-chip resources (see Figure 3-1).
This bus structure enhances the overall system performance by enabling the concurrent
operation of several subsystems of the XC164KM.
The following block diagram gives an overview of the different on-chip components and
of the advanced, high bandwidth internal bus structure of the XC164KM.
PSRAM
2 K by te s
P rogMe m
Flash
6 4 K by te s (8 F de v ic e )
3 2 K by te s (4 F de v ic e )
OCDS
D e b u g Su p p o rt
Osc / PLL RTC WDT
XTAL _{C lo ck Ge n e ra tio n}
DPRAM
2 K by te s
CPU
C 1 6 6 SV2 -C ore
DSRAM
2 K by te s
(8 F de v ic e )
re_Ld_Xu_Bc_ue_sd
C^Eo^Bn ^Ctro l
Interrupt & PEC
Interrupt Bus
P eripheral Data B us
GPT ASC0 ASC1 SSC0 SSC1
T2 ^{(USART) (USART) (SPI) (SPI)}
T3
T4
T5
T6 BRGen BRGen BRGen BRGen
CC2
T7
T8
Port 9
Port 5
Port 3
6
14
13
PORT1
14
Tw in
CAN
AB
Figure 3-1 Block Diagram
mc_xc164km_block.vsd
Data Sheet
14
V1.0, 2005-11