XC167-16 Datasheet, PDF (440/442 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

SYSCON1 6-44 [1]
SYSCON3 6-58 [1]
SYSSTAT 6-45 [1]
T
T0IC 17-9 [2]
T12 18-6 [2]
T12DTC 18-23 [2]
T12MSEL 18-20 [2]
T12PR 18-6 [2]
T13 18-31 [2]
T13PR 18-31 [2]
T1IC 17-9 [2]
T2, T3, T4 14-29 [2]
T2CON 14-15 [2]
T2IC, T3IC, T4IC 14-30 [2]
T3CON 14-4 [2]
T4CON 14-15 [2]
T5, T6 14-54 [2]
T5CON 14-40 [2]
T5IC, T6IC 14-55 [2]
T6CON 14-33 [2]
T7IC 17-9 [2]
T8IC 17-9 [2]
TCTR0 18-41 [2]
TCTR2 18-43 [2]
TCTR4 18-44 [2]
TFR 5-45 [1]
Timer 14-2 [2], 14-31 [2]
Auxiliary Timer 14-15 [2], 14-40 [2]
Concatenation 14-22 [2], 14-45 [2]
Core Timer 14-4 [2], 14-33 [2]
Counter Mode (GPT1) 14-10 [2],
14-39 [2]
Gated Mode (GPT1) 14-9 [2]
Gated Mode (GPT2) 14-38 [2]
Incremental Interface Mode (GPT1)
14-11 [2]
Mode (GPT1) 14-8 [2]
Mode (GPT2) 14-37 [2]
Tools 1-8 [1]
Transmit FIFO ASC 19-9 [2]
Traps 5-43 [1]
XC167-16 Derivatives
Peripheral Units (Vol. 2 of 2)
Keyword Index
TRPCTR 18-63 [2]
TwinCAN
FIFO
base object 22-24 [2]
circular buffer 22-26 [2]
configuration 22-73 [2]
for CAN messages 22-24 [2]
gateway control 22-73 [2]
slave objects 22-26 [2]
frames
counter 22-8 [2]
handling 22-17 [2]
gateway
configuration 22-73 [2]
normal mode 22-29 [2]
shared mode 22-36 [2]
with FIFO 22-33 [2]
initialization 22-40 [2]
interrupts
indication/INTID 22-13 [2],
22-53 [2]
node pointer/request compressor
22-5 [2]
loop-back mode 22-44 [2]
message handling 22-15 [2]
FIFO 22-24 [2]
gateway overview 22-28 [2]
gateway+FIFO 22-33 [2]
normal gateway 22-29 [2]
shared gateway 22-36 [2]
transfer control 22-41 [2]
message interrupts 22-13 [2]
message object
configuration 22-71 [2]
control bits 22-68 [2]
interrupt indication 22-13 [2]
interrupts 22-13 [2]
register description 22-64 [2]
transfer handling 22-17 [2]
node control 22-7 [2]
node interrupts 22-11 [2], 22-12 [2]
node selection 22-71 [2]
overview 22-1 [2]
User’s Manual
i-7
V2.0, 2004-04