XC167-16 Datasheet, PDF (207/442 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

XC167-16 Derivatives
Peripheral Units (Vol. 2 of 2)
Capture/Compare Unit 6 (CAPCOM6)
The reset of TRPF is controlled by the mode control bit TRPM2 (located in the Trap
Control Register TRPCTR). When TRPM2 = 0, TRPF is automatically cleared by HW
when CTRAP returns to the inactive level (CTRAP = 1). When TRPM2 = 1, TRPF must
be reset by SW after CTRAP has become inactive.
The reset of TRPS is controlled by the mode control bits TRPM1 and TRPM0 (located in
the Trap Control Register TRPCTR). A reset of TRPS terminates the Trap State and
returns to normal operation. There are three options selected by TRPM1 and TRPM0.
One is that the Trap State is left immediately when the Trap Flag TRPF is cleared,
without any synchronization to timers T12 or T13. The other two options facilitate the
synchronization of the termination of the Trap State to the count periods of either Timer
T12 or Timer T13. Figure 18-38 gives an overview on the associated operation.
T12 Count
T13 Count
TRPF
TRPS
TRPS
TRPS
CTRAP active
Sync. to T12
Sync. to T13
No sync.
Figure 18-38 Trap State Synchronization (with TRM2 = 0)
MCT05542
User’s Manual
CAPCOM6_X, V2.0
18-62
V2.0, 2004-04