XC167-16 Datasheet, PDF (204/442 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units

XC167-16 Derivatives
Peripheral Units (Vol. 2 of 2)
Capture/Compare Unit 6 (CAPCOM6)
Field
Bits Type Description
EXPH¹⁾
[10:8] rh
Expected Hall Pattern
EXPH is written by a shadow transfer from bitfield
EXPHS. Bitfield EXPH is compared to the sampled
Hall pattern after every detected edge at the Hall
sensor inputs CC6POSx. If the pattern match, a
Correct Hall Event signal is generated, which triggers
further actions.
R
MCMP²⁾
6
rh
[5:0] rh
Reminder Flag
Indicates that the shadow transfer from bitfield
MCMPS to MCMP has been requested by the
selected trigger source. This bit is cleared while
MCMEN = 0 and when the shadow transfer takes
place.
0 No shadow transfer is requested
1 A shadow transfer from MCMPS to MCMP has
been requested but not yet executed
Multi-Channel Modulation Pattern
MCMP contains the output modulation pattern for the
Multi-Channel mode, which can set the
corresponding output to the passive state. It is written
by a shadow transfer from bitfield MCMPS.
0 The output is set to the passive state.
1 The output can deliver the PWM generated by
T12 or T13 (according to register MODCTR).
MCMP[5:0] corresponds to (left to right):
COUT62, CC62, COUT61, CC61, COUT60, CC60.
1) The bits in the bitfields EXPH and CURH correspond to the hall patterns at the input pins CCPOSx (x = 0, 1,
2) in the order (EXPH.2, EXPH.1, EXPH.0), (CURH.2, CURH.1, CURH.0), (CCPOS2, CCPOS.1, CCPOS0).
2) While bit IS.IDLE = 1, bitfield MCMP is cleared.
User’s Manual
CAPCOM6_X, V2.0
18-59
V2.0, 2004-04