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XC167-16 Datasheet, PDF (102/442 Pages) Infineon Technologies AG – 16-Bit Single-Chip Microcontroller with C166SV2 Core Volume 2 (of 2): Peripheral Units | |||
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XC167-16 Derivatives
Peripheral Units (Vol. 2 of 2)
The Analog/Digital Converter
Standard Timing Control
Standard timing control is performed by using two 2-bit fields in register ADC_CON.
Bitfield ADCTC (conversion time control) selects the basic conversion clock (fBC), used
for the operation of the A/D converter. The sample time is derived from this conversion
clock and controlled by bitfield ADSTC. The sample time is always a multiple of 8 fBC
periods. Table 16-3 lists the possible combinations.
Table 16-3 Standard Conversion and Sample Timing Control
ADC_CON.15|14
(ADCTC)
00
01
10
11
A/D Converter
Basic Clock fBC1)
fADC/4
fADC/2
fADC/16
fADC/8
ADC_CON.13|12
(ADSTC)
00
01
10
11
Sample Time tS
tBC Ã 8
tBC Ã 16
tBC Ã 32
tBC Ã 64
Improved Timing Control
To provide a finer resolution for programming of the timing parameters, wider bitfields
have been implemented for timing control (the 2-bit bitfields in register ADC_CON are
disregarded in all cases).
In compatibility mode (with bit ICST = 1), the bitfields in register ADC_CON1 are used
for all conversions.
In enhanced mode (bit MD = 1), the bitfields in register ADC_CTR2 are used for
standard conversions. Injected conversions use the bitfields in register ADC_CTR2IN.
Bitfield ADCTC (conversion time control) selects the basic conversion clock (fBC), used
for the operation of the A/D converter. The sample time is derived from this conversion
clock and controlled by bitfield ADSTC. The sample time is always a multiple of 4 fBC
periods. Table 16-4 lists the possible combinations.
Table 16-4 Improved Conversion and Sample Timing Control
ADCTC
A/D Converter
Basic Clock fBC1)
ADSTC
Sample Time tS
00â0000B = 00H fADC/1
00â0000B = 00H
tBC Ã 8
00â0001B = 01H fADC/2
00â0001B = 01H
tBC Ã 12
00â0010B = 02H fADC/3
00â0010B = 02H
tBC Ã 16
â¦
fADC/(ADCTC + 1) â¦
tBC Ã 4 Ã (ADSTC + 2)
11â1111B = 3FH fADC/64
11â1111B = 3FH
tBC Ã 260
1) The limit values for fBC (see data sheet) must not be exceeded when selecting ADCTC and fADC.
Userâs Manual
ADC_X71, V2.1
16-19
V2.0, 2004-04
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