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TLE8110EE_13 Datasheet, PDF (42/74 Pages) Infineon Technologies AG – Overvoltage, Overtemperature, ESD -Protection
TLE 8110 EE
Smart Multichannel Switch
16 bit SPI Interface
11.3
Electrical Characteristics 16 bit SPI Interface
Electrical Characteristics: 16 bit SPI Interface
3.0V < VCC < 5.5V; 4.5V < VDD < 5.5V, Tj = -40°C to +150°C, all voltages with respect to ground, positive current
flowing into pin
(unless otherwise specified)
Pos. Parameter
Symbol
Limit Values
Unit Conditions
Min. Typ. Max.
Input Characteristics (CS, SCLK, SI)
11.3.1 L level of pin
-0.3 -
S_CS VS_CSl
S_CLK VS_CLKl
S_SI VS_SIl
11.3.2 H level of pin
VCC* -
S_CS VS_CSh
0.4
S_CLK VS_CLKh
S_SI VS_SIh
11.3.3 Hysteresis Input Pins
VS_CShy
20
VS_CLKhy
VS_SIhy
100
11.3.4 Input Pin pull-down Current
IS_CLKh
20
40
a)
IS_SIh
b)
S_CLK IS_CLKl
2.4
-
S_SI IS_SIl
11.3.5 Input Pin pull-up Current
IS_CSh
-4
-
a)
b)
S_CS IS_CSl
-20
-40
Output Characteristics (SO)
VCC* V
0.2
VCC
V
300 mV
85
µA
-
µA
-
μA
-85
μA
-
-
-
VIN=5V
VIN=0.6V1)
VS_CS = 2 V,
VCC=3.3V
VS_CS = 0 V,
VCC=5V
11.3.6
11.3.7
L level output voltage
H level output voltage
VS_SOl
0
-
VS_SOh
Vcc -
-
0.4 V
0.4 V
Vcc
IS_SO = -2 mA
IS_SO = 1.5 mA
11.3.8 Output tristate leakage current
IS_SOoff
-10
-
10 μA
VS_SO = Vcc
Timings
11.3.9 Serial clock frequency
fS_CLK
0
-
11.3.10 Serial clock period
tS_CLK(P)
200
-
11.3.11 Serial clock high time
tSCLK(H)
50
-
11.3.12 Serial clock low time
tSCLK(L)
50
-
11.3.13 Enable lead time (falling CS to rising tCS(lead)
250
-
SCLK)
5
MHz -CL = 50 pF 1)
- ns
1)
- ns
1)
- ns
1)
- ns
1)
11.3.14 Enable lag time (falling SCLK to rising tCS(lag)
CS)
250
-
- ns
1)
11.3.15 Transfer delay time (rising CS to falling tCS(td)
CS)
250
-
- ns
1)
11.3.16 Data setup time (required time SI to
falling SCLK)
tSI(su)
20
-
- ns
1)
11.3.17
11.3.18
Data hold time (falling SCLK to SI)
Output enable time (falling CS to SO
valid)
tSI(h)
tSO(en)
20
-
- ns
1)
-
-
200 ns
CL = 50 pF 1)
Data Sheet
42
Rev. 1.4, 2013-07-02