HYS72V16300GR Datasheet, PDF (3/22 Pages) Infineon Technologies AG – PC133 Registered SDRAM-Modules

HYS 72Vxx3xxGR
PC133 Registered SDRAM-Modules
Pin Definitions and Functions
A0 - A11, A12 Address Inputs (A12 is used for
256Mbit based modules only)
DQMB0 - DQMB7 Data Mask
BA0, BA1
Bank Selects
CS0 - CS3
Chip Select
DQ0 - DQ63 Data Input/Output
REGE*)
Register Enable
“H” or N.C = registered mode
“L” = buffered mode
CB0 - CB7
RAS
CAS
Check Bits
Row Address Strobe
Column Address Strobe
V_DD
V_SS
SCL
Power (+ 3.3 V)
Ground
Clock for Presence Detect
WE
Read/Write Input
SDA
Serial Data Out
CKE0
Clock Enable
N.C.
No Connection
CLK0 - CLK3 Clock Input
–
–
Note : *) To confirm to this specification, motherboards must pull this pin to high state or no connect.
Address Format
Density Organization Memory SDRAMs # of
# of row/bank/ Refresh Period Interval
Banks
SDRAMs columns bits
128 MB 16M × 72 1
16M × 4 18
12/2/10
4k
64 ms 15.6 µs
128 MB 16M × 72 1
16M x 8 9
12/2/10
4k
64 ms 15.6 µs
256 MB 32M x 72 1
32M x 4 18
12/2/11
4k
64 ms 15.6 µs
256 MB 32M x 72 1
32M x 8 9
13/2/10
8k
64 ms 7.8 µs
512 MB 64M × 72 1
64M × 4 18
13/2/11
8k
64 ms 7.8 µs
1 GB 128M × 72 2
64M × 4 36
13/2/11
8k
64 ms 7.8 µs
1 GB 128M × 72 1
128M × 4 18
13/2/12
8k
64ms 7.8 µs
2 GB 256M × 72 2
128M × 4 36
13/2/12
8k
64ms 7.8 µs
INFINEON Technologies
3
2002-07-18