HYS72V16300GR Datasheet, PDF (16/22 Pages) Infineon Technologies AG – PC133 Registered SDRAM-Modules

Byte# Description
HYS 72Vxx3xxGR
PC133 Registered SDRAM-Modules
SPD
Hex
Entry
Value
25
Min. Clock Cycle Time at not
00
CL = 1
supported
26
Max. Data Access Time from not supp.
00
Clock at CL = 1
27
SDRAM Minimum t_RP
15 ns
0F
28
SDRAM Minimum t_RRD
14 ns
0E
29
SDRAM Minimum t_RCD
15 ns
0F
30
SDRAM Minimum t_RAS
37 ns
25
31
Module Bank Density (per 128 MByte 20 20 40 40 80 80 01 01
bank)
256 Mbyte
512 MByte
1024 MByte
32
SDRAM Input Setup Time 1.5 ns
15
33
SDRAM Input Hold Time
0.8 ns
08
34
SDRAM Data Input Setup 1.5 ns
15
Time
35
SDRAM Data Input Hold
0.8 ns
08
Time
36-61 Superset Information
–
00
(may be used in future)
62
SPD Revision
JEDEC 2
12
63
Checksum for Bytes 0 - 62 –
8E 16 2F B9 F2 F3 74 75
64-125 Manufacturer’s Information –
126 Frequency Specification
–
64
127 Details of Clocks
–
8F
128+ Unused Storage Locations –
FF
INFINEON Technologies
16
2002-07-18