HYS72V16300GR Datasheet, PDF (21/22 Pages) Infineon Technologies AG – PC133 Registered SDRAM-Modules

HYS 72Vxx3xxGR
PC133 Registered SDRAM-Modules
each subsequent rising clock edge until the burst length is completed. When the burst has finished,
any additional data supplied to the DQ pins will be ignored.
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
Command NOP Write A NOP NOP NOP NOP NOP NOP NOP
DQ’s
DIN A0 DIN A1 DIN A2 DIN A3 don’t care
The first data element and the Write
are registered on the next clock edge
Reg-DIMM Latency = 1 CLK
Registered DIMM Burst Write Operation (BL = 4)
Extra data is ignored after
termination of a Burst.
SPT03969
INFINEON Technologies
21
2002-07-18