HYS72V16300GR Datasheet, PDF (20/22 Pages) Infineon Technologies AG – PC133 Registered SDRAM-Modules

HYS 72Vxx3xxGR
PC133 Registered SDRAM-Modules
Functional Description
All these PC133 168-pin Registered DIMMs conform to a compatible set of timing and operation
characteristics intended to comply with the 133 MHz standards. The Registered DIMMs achieve
high speed data transfer rate up to 133 MHz, when in “registered mode”. The “registered mode” is
achieved when the REGE input signal is in “high” state or the pin is not connected. Operation in
“buffered mode” (REGE = “low”) needs careful system design to compensate all input signals for the
extra delay time of the register components when in “buffered mode”. “Buffered mode” is limited to
66 Mhz maximum operation frequency.
Registered Mode:
All control and address signals are synchronized with the positive edge of externally supplied clocks
and are registered on-DIMM and hence delayed by one clock cycle in arriving at the SDRAM
devices. The use of the on-board register reduces the capacitive loading of the DIMM on input
control and address signals. The SDRAM device data lines (DQ) are connected directly to the DIMM
tabs through 10 Ohm series resistors. All the following timing diagrams and explanations show
DIMM operation at the tabs, not SDRAM operation.
The picture below depicts an overview of the effect of the Registered Mode on the data outputs
(DQs) for a Read operation. Without the registers, the data is delayed according to the device CAS
latency, in the case two clocks. With the register, the data is delayed according to the device CAS
latency plus an additional clock cycle. This is known as the DIMM CAS latency, and in this example
is four three. The data path can be thought of as a pipeline in which the register effectively lengthens
the pipe by one clock cycle.
Registered DIMM Burst Read Operation (BL = 4)
T0
T1
T2
T3
T4
T5
T6
CLK
Command
Read A NOP NOP NOP NOP NOP NOP
Device
CAS latency = 2
t _CK2, DQ’s
DIMM
CAS latency = 3
t _CK3, DQ’s
DOUT A0 DOUT A1 DOUT A2 DOUT A3
DOUT A0 DOUT A1 DOUT A2 DOUT A3
Added for on-DIMM pipeline register
One Clock _{Reg-DIMM Latency = 1}
SPT03968
In case of a Burst Write Command the data-in is delayed one clock due the op-DIMM pipeline
register also. Therefore, data for the first Burst Write cycle must be applied on the DQ pins on the
next clock cycle after the Write command is issued. the remaining data inputs must be supplied on
INFINEON Technologies
20
2002-07-18