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HYB39L128160AC Datasheet, PDF (27/49 Pages) Infineon Technologies AG – 128-MBIT SYNCHRONOUS LOW-POWER DRAM | |||
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HYB 39L128160AC/T
128-MBit 3.3V Mobile-RAM
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(Burst Length = 4, CAS latency = 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
Command NOP Write A Write B NOP NOP NOP NOP NOP NOP
1 Clk Interval
DQâs
DIN A0 DIN B0 DIN B1 DIN B2 DIN B3
SPT03791
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(Burst Length = 4, CAS latency = 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
Command NOP Write A Read B NOP NOP NOP NOP NOP NOP
CAS
latency = 2
t CK2, DQâs
CAS
latency = 3
t CK3, DQâs
DIN A0 donât care
DOUT B0 DOUT B1 DOUT B2 DOUT B3
DIN A0 donât care donât care
Input data for the Write is ignored.
DOUT B0 DOUT B1 DOUT B2 DOUT B3
Input data must be removed from the DQâs
at least one clock cycle before the Read data
appears on the outputs to avoid data contention.
SPT03719
INFINEON Technologies
27
2003-02
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