HYB39L128160AC Datasheet, PDF (13/49 Pages) Infineon Technologies AG – 128-MBIT SYNCHRONOUS LOW-POWER DRAM

HYB 39L128160AC/T
128-MBit 3.3V Mobile-RAM
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There is also a separate precharge command available. When RAS and WE are low and CAS is
high at a clock edge, it triggers the precharge operation. Three address bits, BA0, BA1 and A10 are
used to define banks as shown in the following list. The precharge command can be imposed one
clock before the last data out for CAS latency = 2 and two clocks before the last data out for CAS
latency = 3. Writes require a time delay W_WR from the last data out to apply the precharge command.
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A10 BA0 BA1
0
0
0 Bank 0
0
0
1 Bank 1
0
1
0 Bank 2
0
1
1 Bank 3
1
x
x all Banks
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Once a burst read or write operation has been initiated, there are several methods used to terminate
the burst operation prematurely. These methods include using another Read or Write Command to
interrupt an existing burst operation, using a Precharge Command to interrupt a burst cycle and
close the active bank, or using the Burst Stop Command to terminate the existing burst operation
but leave the bank open for future Read or Write Commands to the same page of the active bank.
When interrupting a burst with another Read or Write Command care must be taken to avoid DQ
contention. The Burst Stop Command, however, has the fewest restrictions making it the easiest
method to use when terminating a burst operation before it has been completed. If a Burst Stop
command is issued during a burst write operation, then any residual data from the burst write cycle
will be ignored. Data that is presented on the DQ pins before the Burst Stop Command is registered
will be written to the memory.
INFINEON Technologies
13
2003-02