HYB39L128160AC Datasheet, PDF (10/49 Pages) Infineon Technologies AG – 128-MBIT SYNCHRONOUS LOW-POWER DRAM

HYB 39L128160AC/T
128-MBit 3.3V Mobile-RAM
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The default power on state of the mode register is supplier specific and may be undefined. The
following power on and initialization sequence guarantees the device is preconditioned to each
users specific needs. Like a conventional DRAM, the Synchronous DRAM must be powered up and
initialized in a predefined manner. 9_DD must be applied before or at the same time as 9_DDQ to the
specified voltage when the input signals are held in the “NOP” or “DESELECT” state. The power on
voltage must not exceed 9_DD + 0.3 V on any of the input pins or VDD supplies. The CLK signal must
be started at the same time. After power on, an initial pause of 200 µs is required followed by a
precharge of all banks using the precharge command. To prevent data contention on the DQ bus
during power on, it is required that the DQM and CKE pins be held high during the initial pause
period. Once all banks have been precharged, the Mode Register Set Command must be issued to
initialize the Mode Register. A minimum of eight Auto Refresh cycles (CBR) are also required.These
may be done before or after programming the Mode Register. Failure to follow these steps may lead
to unpredictable start-up modes.
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The Mode Register designates the operation mode at the read or write cycle. This register is divided
into 4fields. A Burst Length Field to set the length of the burst, an Addressing Selection bit to
program the column access sequence in a burst cycle (interleaved or sequential), and a CAS
LatencyÃField to set the access time at clock cycle, an The mode set operation must be done before
any activate command after the initial power up. Any content of the mode register can be altered by
re-executing the mode set command. All banks must be in precharged state and CKE must be high
at least one clock before the mode set operation. After the mode register is set, a Standby or NOP
command is required. Low signals of RAS, CAS, and WE at the positive edge of the clock activate
the mode set operation. Address input data at this timing defines parameters to be set as shown in
the previous table. BA0 and BA1 have to be set to “0” to enter the Mode Register.
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When RAS is low and both CAS and WE are high at the positive edge of the clock, a RAS cycle
starts. According to address data, a word line of the selected bank is activated and all of sense
amplifiers associated to the wordline are set. A CAS cycle is triggered by setting RAS high and CAS
low at a clock timing after a necessary delay, W_RCD, from the RAS timing. WE is used to define either
a read (WE = H) or a write (WE = L) at this stage.
SDRAM provides a wide variety of fast access modes. In a single CAS cycle, serial data read or
write operations are allowed at up to a 133 MHz data rate. The numbers of serial data bits are the
burst length programmed at the mode set operation, i.e., one of 1, 2, 4, 8 and full page. Column
addresses are segmented by the burst length and serial data accesses are done within this
boundary. The first column address to be accessed is supplied at the CAS timing and the
subsequent addresses are generated automatically by the programmed burst length and its
sequence. For example, in a burst length of 8 with interleave sequence, if the first address is ‘2’,
then the rest of the burst sequence is 3, 0, 1, 6, 7, 4, and 5.
Full page burst operation is only possible using the sequential burst type and page length is a
function of the I/O organisation and column addressing. Full page burst operation does not self
terminate once the burst length has been reached. In other words, unlike burst length of 2, 4 and 8,
full page burst continues until it is terminated using another command.
INFINEON Technologies
10
2003-02