HYB39S512400AT Datasheet, PDF (24/28 Pages) Infineon Technologies AG – 512-Mbit Synchronous DRAM

4.2
AC Characteristics
Table 12 AC Characteristics¹⁾²⁾³⁾
Parameter
Symbol
Clock and Clock Enable
Clock Cycle Time
t_CK
CAS Latency = 3
CAS Latency = 2
Clock Frequency
t_CK
CAS Latency = 3
CAS Latency = 2
Access Time from Clock
t_AC
CAS Latency = 3
CAS Latency = 2
Clock High Pulse Width
t_CH
Clock Low Pulse Width
t_CL
Transition time
t_T
Setup and Hold Times
Input Setup Time
t_IS
Input Hold Time
t_IH
CKE Setup Time
t_CK
CKE Hold Time
t_CKH
Mode Register Set-up to Active t_RSC
delay
Power Down Mode Entry Time t_SB
Common Parameters
Row to Column Delay Time
t_RCD
Row Precharge Time
t_RP
Row Active Time
t_RAS
Row Cycle Time
t_RC
Row Cycle Time during Auto
t_RFC
Refresh
Activate(a) to Activate(b)
t_RRD
Command period
CAS(a) to CAS(b) Command t_CCD
period
Refresh Cycle
Refresh Period (8192 cycles)
Self Refresh Exit Time
Data Sheet
t_REF
t_SREX
HYB 39S512[40/80/16]0AT(L)
512-Mbit Synchronous DRAM
Electrical Characteristics
–7
–7.5
–8
Unit
PC133-222 PC133-333 PC100-222
min. max. min. max. min. max.
Notes
7
–
7.5 –
8
–
ns
7.5 –
10 –
10 –
ns
–
143 –
133 –
125 MHz
–
133 –
100 –
100 MHz
–
5.4 –
5.4 –
6
ns
3)4)5)
–
5.4 –
6
–
6
ns
2.5 –
2.5 –
3
–
ns
2.5 –
2.5 –
3
–
ns
0.3 1.2 0.3 1.2 0.5 10 ns
1.5 –
1.5 –
2
–
ns
6)
0.8 –
0.8 –
1
–
ns
6)
1.5 –
1.5 –
2
–
ns
6)
0.8 –
0.8 –
1
–
ns
6)
2
–
2
–
2
–
CLK
0
7
0
7.5 0
8
ns
15 –
20 –
20 –
ns
7)
15 –
20 –
20 –
ns
7)
37 100k 45 100k 48 100k ns
7)
60 –
67 –
70 –
ns
7)
63
67
70
ns
14 –
15 –
16 –
ns
7)
1
–
1
–
1
–
CLK
–
64 –
1
–
1
24
64 –
–
1
64 ms
CLK
Rev. 1.3, 2004-03
10082003-L1GD-PVI5