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HYB39S512400AT Datasheet, PDF (24/28 Pages) Infineon Technologies AG – 512-Mbit Synchronous DRAM
4.2
AC Characteristics
Table 12 AC Characteristics1)2)3)
Parameter
Symbol
Clock and Clock Enable
Clock Cycle Time
tCK
CAS Latency = 3
CAS Latency = 2
Clock Frequency
tCK
CAS Latency = 3
CAS Latency = 2
Access Time from Clock
tAC
CAS Latency = 3
CAS Latency = 2
Clock High Pulse Width
tCH
Clock Low Pulse Width
tCL
Transition time
tT
Setup and Hold Times
Input Setup Time
tIS
Input Hold Time
tIH
CKE Setup Time
tCK
CKE Hold Time
tCKH
Mode Register Set-up to Active tRSC
delay
Power Down Mode Entry Time tSB
Common Parameters
Row to Column Delay Time
tRCD
Row Precharge Time
tRP
Row Active Time
tRAS
Row Cycle Time
tRC
Row Cycle Time during Auto
tRFC
Refresh
Activate(a) to Activate(b)
tRRD
Command period
CAS(a) to CAS(b) Command tCCD
period
Refresh Cycle
Refresh Period (8192 cycles)
Self Refresh Exit Time
Data Sheet
tREF
tSREX
HYB 39S512[40/80/16]0AT(L)
512-Mbit Synchronous DRAM
Electrical Characteristics
–7
–7.5
–8
Unit
PC133-222 PC133-333 PC100-222
min. max. min. max. min. max.
Notes
7
–
7.5 –
8
–
ns
7.5 –
10 –
10 –
ns
–
143 –
133 –
125 MHz
–
133 –
100 –
100 MHz
–
5.4 –
5.4 –
6
ns
3)4)5)
–
5.4 –
6
–
6
ns
2.5 –
2.5 –
3
–
ns
2.5 –
2.5 –
3
–
ns
0.3 1.2 0.3 1.2 0.5 10 ns
1.5 –
1.5 –
2
–
ns
6)
0.8 –
0.8 –
1
–
ns
6)
1.5 –
1.5 –
2
–
ns
6)
0.8 –
0.8 –
1
–
ns
6)
2
–
2
–
2
–
CLK
0
7
0
7.5 0
8
ns
15 –
20 –
20 –
ns
7)
15 –
20 –
20 –
ns
7)
37 100k 45 100k 48 100k ns
7)
60 –
67 –
70 –
ns
7)
63
67
70
ns
14 –
15 –
16 –
ns
7)
1
–
1
–
1
–
CLK
–
64 –
1
–
1
24
64 –
–
1
64 ms
CLK
Rev. 1.3, 2004-03
10082003-L1GD-PVI5