HYB39S512400AT Datasheet, PDF (23/28 Pages) Infineon Technologies AG – 512-Mbit Synchronous DRAM

HYB 39S512[40/80/16]0AT(L)
512-Mbit Synchronous DRAM
Electrical Characteristics
Table 11 I_DD Specifications
Symbol –7
Typ.
Max.
–7.5
Typ.
Max.
–8
Typ.
Max.
Unit Note/Test
Condition ¹⁾
I_DD1
131
145
123
145
95
110
mA
2) 3)
I_DD2P
0.6
3
0.6
3
0.6
3
mA ²⁾
I_DD2N
25
31
23
31
19
25
mA ²⁾
I_DD3N
27
35
26
35
21
30
mA ²⁾
I_DD3P
2
4
2
4
2
4
mA ²⁾
I_DD4
102
123
97
123
79
100
mA
2) 3)
I_DD5
270
300
255
300
240
270
mA
t_RFC = t_RFC(min.) ⁴⁾
I_DD6
2.1
4
2.1
4
2.1
4
mA Standard
1) T_A = 0 to 70 °C; V_SS = 0 V, V_DD, V_DDQ = +3.3 V ± 0.3 V
2) These parameters depend on the cycle rate. All values are measured at 133 MHz for “-7” and “-7.5” and at 100 MHz for
“-8” components with the outputs open. Input signals are changed once during t_ck.
3) These parameters are measured with continuous data stream during read access and all DQ toggling. CL=3 and BL=4 is
assumed and the V_DDQ current is excluded.
4) t_RFC = t_RFC(min.) “burst refresh”.
Data Sheet
23
Rev. 1.3, 2004-03
10082003-L1GD-PVI5