HYB39S512400AT Datasheet, PDF (12/28 Pages) Infineon Technologies AG – 512-Mbit Synchronous DRAM

2.3
Block Diagrams
HYB 39S512[40/80/16]0AT(L)
512-Mbit Synchronous DRAM
Pin Configuration
C olum n Address
C ounter
C olum n A ddresses
A 0 - A 9 , A P,,A 1 1 ,A 1 2
BA0, BA1
R ow Addresses
A0 - A12,
BA0, BA1
C olum n Address
B u ffe r
R ow Address
B u ffe r
Refresh Counter
Row
Decoder
M em ory
A rray
Bank 0
8192
x 4096
x 4 Bit
Row
Decoder
M em ory
A rray
Bank 1
8192
x 4096
x 4 Bit
In p ut B u ffer O u tpu t B uffe r
DQ0 - DQ3
Row
Decoder
M em ory
A rray
Bank 2
8192
x 4096
x 4 Bit
R ow
Decoder
M em ory
A rray
Bank 3
8192
x 4096
x 4 B it
C ontrol Logic &
Tim ing G enerator
Figure 2 Block Diagram for 128M × 4 SDRAM ( 13 / 12 / 2 addressing)
Data Sheet
12
Rev. 1.3, 2004-03
10082003-L1GD-PVI5