HYB39S512400AT Datasheet, PDF (15/28 Pages) Infineon Technologies AG – 512-Mbit Synchronous DRAM

HYB 39S512[40/80/16]0AT(L)
512-Mbit Synchronous DRAM
Functional Description
3
Functional Description
3.1
Operation Definition
All SDRAM operations are defined by states of control signals CS, RAS, CAS, WE, and DQM at the positive edge
of the clock. The following list shows the truth table for the operation commands.
Table 4 Truth Table: Operation Command
Operation
Bank Active
Devics State
Idle ³⁾
CKE CKE DQM BA0 AP= Addr CS
n-1¹⁾²⁾ n^{1)2) 1)2)}
BA1¹⁾²⁾ A10^{1)2) 1)2)}
1)2)
H
XX V
V
VL
Bank Precharge Any
H
XX V
L
XL
Precharge All
Write
Write with Autopre-
charge
Any
Active ³⁾
Active ³⁾
H
XX X
H
XL
H
XX V
L
VL
H
XX V
H
VL
Read
Read with Autopre-
charge
Active ³⁾
Active ³⁾
H
XX V
L
VL
H
XX V
H
VL
Mode Register Set Idle
H
XX V
V
VL
No Operation
Any
H
XX X
X
XL
Burst Stop
Active
H
XX X
X
XL
Device Deselect Any
H
XX X
X
XH
Auto Refresh
Idle
H
HX X
X
XL
Self Refresh Entry Idle
H
LX X
X
XL
Self Refresh Exit Idle
L
HX X
X
XH
(Self Refr.)
L
Clock Suspend
Entry
Active
L
HX X
X
XX
Power Down Entry Idle
(Precharge or active
standby)
Active ⁴⁾
H
H
LX X
X
X
L
Clock Suspend Exit Active
L
HX X
X
XX
Power Down Exit Any
L
HX X
X
XH
(Power Down)
L
Data Write/Output Active
Enable
H
XL
X
X
XX
Data Write/Output Active
Disable
H
XH X
X
XX
RAS CAS WE
1)2) 1)2) 1)2)
L HH
L HL
L HL
HL L
HL L
HL H
HL H
LLL
HHH
HHL
XXX
LLH
LLH
XXX
HHX
XXX
XXX
HHH
XXX
XXX
HHL
XXX
XXX
1) V = Valid, x = Don’t Care, L = Low Level, H = High Level
2) CKEn signal is input level when commands are provided, CKEn-1 signal is input level one clock before the commands are
provided.
3) This is the state of the banks designated by BA0, BA1 signals.
4) Power Down Mode can not be entered in a burst cycle. When this command asserted in the burst mode cycle device is in
clock suspend mode.
Data Sheet
15
Rev. 1.3, 2004-03
10082003-L1GD-PVI5