HYB39S512400AT Datasheet, PDF (17/28 Pages) Infineon Technologies AG – 512-Mbit Synchronous DRAM

HYB 39S512[40/80/16]0AT(L)
512-Mbit Synchronous DRAM
Functional Description
MR
Mode Register Definition
(BA[1:0] = 00_B)
BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
A13
0
0
MODE
CL
BT
BL
reg. addr
w
w
w
w
Field
BL
Bits Type Description
[2:0] w
Burst Length
Number of sequential bits per DQ related to one read/write command
Note: All other bit combinations are RESERVED
000 1
001 2
010 4
011 8
111 Full Page
BT
3
w
Burst Type
See Table 5 for internal address sequence of low order address bits.
0 Sequential
1 Interleaved
CL
[6:4] w
CAS Latency
Number of full clocks from read command to first data valid window.
Note: All other bit combinations are RESERVED
Operating [13:7] w
Mode
010 2
011 3
Operating Mode
Note: All other bit combinations are RESERVED.
0 burst read / burst write
1 burst read / single write
Data Sheet
17
Rev. 1.3, 2004-03
10082003-L1GD-PVI5