HYB39S512400AT Datasheet, PDF (10/28 Pages) Infineon Technologies AG – 512-Mbit Synchronous DRAM

2
Pin Configuration
2.1
Signal Pin Description
HYB 39S512[40/80/16]0AT(L)
512-Mbit Synchronous DRAM
Pin Configuration
Table 3 Signal Pin Description
Pin
Type Signal Polarity Function
CLK
Input Pulse Positive Clock Input
Edge The system clock input. All of the SDRAM inputs are sampled on the rising
edge of the clock.
CKE
Input
Level Active
High
Clock Enable
Activates the CLK signal when high and deactivates the CLK signal when
low, thereby initiating either the Power Down mode, Suspend mode, or the
Self Refresh mode.
CS
Input Pulse Active Chip Select
Low CS enables the command decoder when low and disables the command
decoder when high. When the command decoder is disabled, new
commands are ignored but previous operations continue.
RAS
CAS
WE
Input
Pulse Active
Low
Command Signals
When sampled at the positive rising edge of the clock, CAS, RAS, and WE
define the command to be executed by the SDRAM.
A0 - A12 Input Level –
Address Inputs
During a Bank Activate command cycle, A0-A12 define the row address
(RA0-RA12) when sampled at the rising clock edge.
During a Read or Write command cycle, A0-An define the column address
(CA0-CAn) when sampled at the rising clock edge. CAn depends upon the
SDRAM organization:
64M x4 SDRAM CAn = CA9, CA11 (Page Length = 2048 bits)
32M x8 SDRAM CAn = CA9 (Page Length = 1024 bits)
16M x16 SDRAM CAn = CA8 (Page Length = 512 bits)
In addition to the column address, A10 (= AP) is used to invoke the
autoprecharge operation at the end of the burst read or write cycle. If A10
is high, autoprecharge is selected and BA0, BA1 defines the bank to be
precharged. If A10 is low, autoprecharge is disabled.
During a Precharge command cycle, A10 (= AP) is used in conjunction
with BA0 and BA1 to control which bank(s) to precharge. If A10 is high, all
four banks will be precharged regardless of the state of BA0 and BA1. If
A10 is low, then BA0 and BA1 are used to define which bank to precharge.
BA0, BA1 Input Level –
Bank Select
Bank Select Inputs. Bank address inputs selects which of the four banks a
command applies to.
DQx
Input Level –
Output
Data Input/Output
Data Input/Output pins operate in the same manner as on EDO or FPM
DRAMs.
Data Sheet
10
Rev. 1.3, 2004-03
10082003-L1GD-PVI5