TC1793 Datasheet, PDF (166/189 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller

5.3.12 EBU Timings
TC1793
Electrical ParametersAC Parameters
5.3.12.1 BFCLKO Output Clock Timing
V_SS = 0 V;V_DD = 1.3 V ± 5%; V_DDEBU = 2.5 V ± 5% and 3.3 V ± 5%,;
C_L = 35 pF
Table 40 BFCLK0 Output Clock Timing Parameters¹⁾
Parameter
Symbol
Min.
Values
Typ. Max.
Unit Note /
Test Con
dition
BFCLKO clock period
t_BFCLKO CC 13.33²⁾ –
–
ns –
BFCLKO high time
t₅
CC 3
–
–
ns –
BFCLKO low time
t₆
CC 3
–
–
ns –
BFCLKO rise time
t₇
CC –
–
3
ns –
BFCLKO fall time
t_{8 CC}
–
–
3
BFCLKO duty cycle t₅/(t₅ + t₆)³⁾ DC
35
50 55
1) Not subject to production test, verified by design/characterization.
ns –
%–
2) The PLL jitter characteristics add to this value according to the application settings. See the PLL jitter
parameters.
3) The PLL jitter is not included in this parameter. If the BFCLKO frequency is equal to f_CPU, the K divider has to
be regarded.
t_BFCLKO
BFCLKO 0.5 V_DDP05
t₅
t₆
t₈
0.9 V_DD
t₇
0.1 V_DD
MCT04883_mod
Figure 24 BFCLKO Output Clock Timing
5.3.12.2 EBU Asynchronous Timings
V_SS = 0 V;V_DD = 1.3 V ± 5%; V_DDEBU = 2.5 V ± 5% and 3.3 V ± 5%, Class B pins;
C_L = 35 pF for address/data; C_L = 40pF for the control lines.
For each timing, the accumulated PLL jitter of the programed duration in number of clock
periods must be added separately. Operating conditions apply and C_L = 35 pF.
Data Sheet
159
V 1.2, 2014-05