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TC1793 Datasheet, PDF (14/189 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller | |||
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TC1793
Summary of Features
â 64-bit Cross Bar Interconnect between CPU, Flash and Data Memory
â 32-bit System Peripheral Bus (SPB) for on-chip peripheral and functional units
â One bus bridge (SFI Bridge)
⢠Versatile On-chip Peripheral Units
â Two Asynchronous/Synchronous Serial Channels (ASC) with baud rate generator,
parity, framing and overrun error detection
â Four High-Speed Synchronous Serial Channels (SSC) with programmable data
length and shift direction
â Four SSC Guardian (SSCG) modules, one for each SSC
â Two serial Micro Second Bus interfaces (MSC) for serial port expansion to external
power devices
â Two High-Speed Micro Link interfaces (MLI) for serial inter-processor
communication
â One External Bus Interface (EBU) supporting different memories: asynchronous
memories e.g. SRAM, peripheral devices; synchronous devices e.g. burst NOR
flash, PSRAM; and DDR NOR flash e.g. LPDDR-NVM (Jedec 42.2), ONFI 2.0
(limited frequency at 1.8 V I/O supply)
â One MultiCAN Module with 4 CAN nodes and 128 free assignable message
objects for high efficiency data handling via FIFO buffering and gateway data
transfer (one CAN node supports TTCAN functionality)
â One FlexRayTM module with 2 channels (E-Ray).
â Two General Purpose Timer Array Modules (GPTA) with additional Local Timer
Cell Array (LTCA2) providing a powerful set of digital signal filtering and timer
functionality to realize autonomous and complex Input/Output management
â Two Capture / Compare 6 modules
â Two General Purpose 12 Timer Units (GPT120 and GPT121)
⢠44 analog input lines for ADC
â 4 independent kernels (ADC0, ADC1, and ADC2)
â Analog supply voltage range from 3.3 V to 5 V (single supply)
⢠4 different FADC input channels
â channels with impedance control and overlaid with ADC1 inputs
â Extreme fast conversion, 21 cycles of fFADC clock
â 10-bit A/D conversion (higher resolution can be achieved by averaging of
consecutive conversions in digital data reduction filter)
⢠8 digital input lines for SENT
â communication according to the SENT specification J2716 FEB2008
⢠221 digital general purpose I/O lines (GPIO)
⢠Digital I/O ports with 3.3 V capability
⢠On-chip debug support for OCDS Level 1 (CPU, PCP, DMA, On Chip Buses)
⢠Dedicated Emulation Device chip available (TC1793ED)
â multi-core debugging, real time tracing, and calibration
â four/five wire JTAG (IEEE 1149.1) or two wire DAP (Device Access Port) interface
⢠Power Management System
Data Sheet
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V 1.2, 2014-05
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