ICS1523 Datasheet, PDF (9/21 Pages) Integrated Circuit Systems – Video Clock Synthesizer with I2C Programmable Delay

ICS1523
Video Clock Synthesizer with I²C Programmable Delay
The DPA Resolution Select register (0x5:0~1) is
double-buffered. Working registers are loaded only
after a DPA software reset (0x8=xA)
For more details, See Figure 11.2
Section 6 OSC Divider and REF
The ICS1523 accepts a single-ended clock on pin 12,
the OSC input. The period of this input signal becomes
the high time of the REF signal and the low time is
controlled by 0x7:0~6.
The resulting REF signal can be used as an input to the
PLL’s phase detector to allow the ICS1523 to
synthesize frequencies without an HSYNC input when
0x7:7=1.
This REF signal may also be output on the LOCK/REF
pin (14) when 0x0:6-7 = 11
Table 6-1 REF Functionality
Parameter
Value
REF Frequency
(Input Osc Frequency) *
[(0x7: 6~0) + 2]
REF High Time
Input OSC Period
REF Low Time
[(0x7: 6~0) + 1] * Input
OSC Period
Minimum OSC Divider 3 (0x7:6~0 = 000001)
Maximum OSC Divider 129 (0x7:6~0 = 111111)
RESERVED OSC Divider 0 (0x7:6~0 = 000000)
While the internal loop filter works well for most
applications, IDT still recommends the implementation
of an external filter network on all designs.
Implementing the external loop filter gives the system
engineer flexibility to add external filter functionality if
without having to alter the PCB.
7.1 External Filter Recommendations
IDT recommends the following as a general purpose
external loop filter:
CS = 3300 pF
RS = 6.8 kΩ
CP = 33 pF
Special considerations must be made in selecting loop
capacitors CS and CP.
Section 8 PLL Parameter Settings
Settings for all standard VESA video modes are
provided by IDT as a starting point for the systems
engineer. These files are in human readable text files
(*.ics files) and come bundled within the ICS1523
Register Editor Tool.
This tool directly drives the ICS1523EB Evaluation
Board and can be downloaded from the IDT web site.
Section 7 Loop Filter
The ICS1523 contains an internal loop filter, but also
supports the use of an external loop filter configured as
in Figure 7-1. Selection between these two filters is
controlled by 0x4:7. The external filter is selected when
4:7=0; internal filter is selected with a 1.
Figure 7-1 External Loop Filter
Pin 8
CS
RS
CP
Pin 9
MDS ICS1523 Z
9
Integrated Device Technology, Inc. Tech Support: www.idt.com/go/clockhelp
Revision 052407