ICS1523 Datasheet, PDF (16/21 Pages) Integrated Circuit Systems – Video Clock Synthesizer with I2C Programmable Delay

ICS1523
Video Clock Synthesizer with I²C Programmable Delay
12.2 Timing for 0x0:2=1
Figure 12-3 0x0:2=1 Timing Diagram
Table 12-3 0x0:2=1 Timing Values
Symbol Parameter
T2 HSYNC Low to FUNC High Delay
T3 HSYNC Low to PECL CLK+ High Delay
(DPA Offset = 0)
T4 PECL Clock to SSTL_3 Clock Delay
T5 PECL Clock to FUNC Delay
T6 PECL Clock to PECL/2 Clock
T7 PECL Clock to SSTL_3 CLK/2 Delay
T8 PECL Clock High Time
Minimum
-
0
0.6
0.6
0.4
-
Typical
T8 + T3
10
0.2
1.0
1.0
0.9
0.5
Maximum
-
0.6
1.6
1.6
1.2
-
Units
ns
ns
ns
ns
ns
ns
UI
MDS ICS1523 Z
16
Integrated Device Technology, Inc. Tech Support: www.idt.com/go/clockhelp
Revision 052407