ICS1523 Datasheet, PDF (11/21 Pages) Integrated Circuit Systems – Video Clock Synthesizer with I2C Programmable Delay

ICS1523
Video Clock Synthesizer with I²C Programmable Delay
9.4 PECL Example
Determine V_OL and V_OH for target device, as follows
(see also Figure 9-1):
1. Choose Z_O
2. RA = (VCC * Z_O) / VOH
3. RB = (Z_O * RA) / (RA - Z_O)
4. RSET=(16.661E-3 -(VCC/RA)+(VOL/RA)+(VOL/RB))
2.4E-6
For more detailed equations regarding PECL
termination, please see the MAN09 application note on
the IDT web site.
Section 10 SSTL_3 Outputs
The ICS1523 incorporates SSTL_3 outputs on FUNC
(pin 15), CLK/2 (pin 16), and CLK (pin 17).
10.1 Unterminated Outputs
In the ICS1523, unterminated SSTL_3 output pins
display exponential transitions similar to those of
rectangular pulses presented to RC loads. The 10 to
90% rise time is typically 1.6 ns, and the corresponding
fall time is typically 700 ps. This asymmetry and
external capacitive loading contribute to duty cycle
distortion at higher output frequencies. Typically, no
termination is required for either the LOCK/REF,
FUNC, and CLK/2 outputs. The CLK output works up to
approximately 135 MHz, and normally requires no
termination.
10.2 Terminated Outputs
SSTL_3 outputs are intended to be terminated into low
impedances to reduce the effect of external circuit
capacitance. Use of transmission line techniques
enables use of longer traces between source and
driver without increasing ringing due to reflections.
Where external capacitance is minimal and substantial
voltage swing is required to meet LVTTL V_IH and V_OL
requirements, the intrinsic rise and fall times of
ICS1523 SSTL_3 outputs are only slightly improved by
termination in a low impedance.
Figure 10-1 SSTL_3 Outputs
VDD
ICS1523
SSTL_3 Output ^330Ω
150Ω
Single
LVTTL
Load
The ICS1523s SSTL_3 output source impedance is
typically less than 60Ω. Termination impedance of 100Ω
reduces output swing by less than 30% which is more
than enough to drive a single LVTTL load.
10.3 Using SSTL_3 Outputs with CMOS
or LVTTL Inputs
Per EIA/JESD8-8, SSTL_3 outputs are intended to
provide a moderate voltage swing across a
low-impedance load at the end of a transmission line.
However, if an SSTL_3 output is connected directly to a
destination LVTTL-compatible input, it can provide
nearly rail-to-rail swings (from 0 to 3.3 V). The
equivalent source impedance of these outputs is
typically 30 to 50Ω. The FUNC and LOCK/REF signals
are both at the input HSYNC frequency rate. As a
result, if these signals are directly connected to a
destination LVTTL-compatible input, this direct
connection does not typically result in signal
degradation.
The CLK and CLK/2 signals operate at much higher
frequency rates. and if they are directly connected to a
destination LVTTL-compatible input, they can exhibit
distortion. For example, their waveforms can appear as
though some shunt capacitance is present across the
output load. This equivalent RC effect limits the highest
frequency at which the SSTL_3 outputs can be used.
For these applications, the PECL outputs must be used
instead.
IDT recommends traces less than 3 cm for all
high-frequency signals.
MDS ICS1523 Z
11
Integrated Device Technology, Inc. Tech Support: www.idt.com/go/clockhelp
Revision 052407