ICS1523 Datasheet, PDF (15/21 Pages) Integrated Circuit Systems – Video Clock Synthesizer with I2C Programmable Delay

ICS1523
Video Clock Synthesizer with I²C Programmable Delay
12.1 Timing for 0x0:2=0
Figure 12-2 0x0:2=0 Timing Diagram
Table 12-2 0x0:2=0 Timing Values
Symbol Parameter
Minimum
T2 HSYNC High to FUNC High
(DPA Offset = 0)
T3 HSYNC High to PECL CLK+ High
-
(DPA Offset = 0)
T4 PECL Clock Low to SSTL_3 Clock Low
0
Delay
T5 PECL Clock Low to FUNC High Delay
0.6
T6 PECL Clock Low to PECL/2 High Clock
0.6
T7 PECL Clock Low to SSTL_3 CLK/2 Delay
0.4
T8 PECL Clock High Time
-
Typical
T8 + T3
7
0.2
1.0
1.0
0.9
0.5
Maximum
-
0.6
1.6
1.6
1.2
-
Units
ns
ns
ns
ns
ns
ns
UI
MDS ICS1523 Z
15
Integrated Device Technology, Inc. Tech Support: www.idt.com/go/clockhelp
Revision 052407