ICS1523 Datasheet, PDF (17/21 Pages) Integrated Circuit Systems – Video Clock Synthesizer with I2C Programmable Delay

ICS1523
Video Clock Synthesizer with I²C Programmable Delay
12.3 HSYNC to REF Timing
Figure 12-4 HSYNC to REF Timing Diagram
HSYNC
Reg0:2 = 1
t0
t1
REF
HSYNC
Reg0:2 = 0
t1
t0
REF
Table 12-4 HSYNC to REF Timing Diagram
Symbol Parameter
T₀ HSYNC Low to REF Delay
T₁ HSYNC High to REF Delay
Minimum
6
3.5
Typical
7.5
4.3
Maximum
8.5
6
Units
ns
ns
12.4 CLK/2 Timing for Odd and Even Feedback Divider
Figure 12-5 CLK/2: Even versus Odd
FUNC
Even - Reg2:0=0
CLK/2
Odd - Reg2:0=1
CLK/2
For simplicity, the waveforms drawn show only the identical PECL CLK/2+ and the SSTL_3 CLK/2 signals. CLK/2-
is the compliment of the CLK/2+ signal.
Note that regardless of the CLK\2 phase at the assertion of FUNC, the clocks always have the same phase at the
fall of FUNC, regardless of 0x2
MDS ICS1523 Z
17
Integrated Device Technology, Inc. Tech Support: www.idt.com/go/clockhelp
Revision 052407