ICS1523 Datasheet, PDF (12/21 Pages) Integrated Circuit Systems – Video Clock Synthesizer with I2C Programmable Delay

ICS1523
Video Clock Synthesizer with I²C Programmable Delay
Section 11 Programming
11.1 Industry-Standard I²C Serial Bus: Data Format
Figure 11-1 ICS1523 Data Format for I²C 2-Wire Serial Bus
Write Procedure for Single Re gis ter
MSB
LSB
S0 1 0 0 1 1 X0A
A
Device address
Register Index
Data
A Stop
Re ad Proce dure for Single Re gis te r
MSB
LSB
S0 1 0 0 1 1 X0A
MSB
LSB
A S0 1 0 0 1 1 X1A
Device address
Register Index
Device address
Repeat START
Write Procedure for M ultiple Regis te rs (Note 1)
MSB
LSB
S0 1 0 0 1 1 X0A
A
A
Device address
Register Index
Data
Data
A Stop
NO Acknow ledge
A
Data
A Stop
Re ad Proce dure for M ultiple Re gis te rs (Note 1)
MSB
LSB
MSB
LSB
S0 1 0 0 1 1 X0A
A S0 1 0 0 1 1 X1A
A
Device address
Register Index
Device address
Data
Repeat START
Legend
All values are sent with the most-significant bit (MSB) first and least-significant bit (LSB) last.
R = Read = 1
W = Write = 0
S = Start (SDA goes low when SCL was high, then SCL goes low too)
A = ACK = Acknowledge = 0
A = ACK = No Acknowledge = 1
X = Bit value that equals logic state of SBADR pin.
A Stop
Data
NO Acknow ledge
= (Dashed Line) Multiple transactions
Bus Master drives signal to ICS1523
ICS1523 (Slave Device) drives signal to Bus Master
Note:
• 1 - Lower nibble of the I²C register automatically increments after each successive data byte is written to
or read from the ICS1523.
• 2 - Upper nibble of the I²C register does not automatically increment, and the software must explicitly
re-address the ICS1523. The software:
– Must NOT just index 0 and then do all the I/O as one-byte transactions.
– Must break the transactions into at least two separate bus transactions:
(1) 00 to 08 (2) 10 to 12
MDS ICS1523 Z
12
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Revision 052407