ICS1523 Datasheet, PDF (7/21 Pages) Integrated Circuit Systems – Video Clock Synthesizer with I2C Programmable Delay

ICS1523
Video Clock Synthesizer with I²C Programmable Delay
4.1 Register Set Summary (continued)
Reg.
Index
0x6
Name Access
Output R / W
Enables
Bit Name
OE_Pck
OE_Tck
OE_P2
OE_T2
OE_F
Ck2_Inv
Out_Scl
Bit #
0
1
2
3
4
5
6-7
Reset
Value
0
0
0
0
0
0
0
Description
Output Enable for PECL CLK (Pins 20, 21)
0=High Z, 1=Enabled
Output Enable for STTL_3 CLK (Pin 17)
0=High Z, 1=Enabled
Output Enable for PECL CLK/2 (Pins 22, 23)
0=High Z, 1=Enabled
Output Enable for STTL_3 CLK/2 (Pin 16)
0=High Z, 1=Enabled)
Output Enable for STTL_3 FUNC Output (Pin15)
0=High Z, 1=Enabled
CLK/2 Invert (0=Not Inverted, 1= Inverted)
CLK Scaler (pin 17)
Bit 7, 6 = (00 = ÷ 1, 01 = ÷ 2, 10 = ÷ 4, 11 = ÷ 8)
See Section 5, “Register Set Details”
Notes
0x7
Osc_Div R / W
Osc_Div 0-6
0-6
In-Sel
7
0 Osc Divider modulus
See Section 6, “OSC Divider and REF”
1 Input Select
0=HSYNC Input, 1=Osc Divider
0x8
Reset Write
DPA
0-3
x Writing xAh resets DPA and loads working 0x5
PLL
4-7
x Writing 5xh resets PLL and loads working 0x1- 0x3
0x10 Chip Ver Read
Chip Ver 0-7
17 Chip Version 23 Dec (17h) as in 1523
0x11 Chip Rev Read
Chip Rev 0-7
01 Initial value 01h. Value Increments with each all-layer change.
0x12 Rd_Reg Read
Reserved
0
PLL_Lock
1
Reserved 2-7
N/A Reserved
N/A PLL Lock Status
0=Unlocked, 1=Locked
0 Reserved
MDS ICS1523 Z
7
Integrated Device Technology, Inc. Tech Support: www.idt.com/go/clockhelp
Revision 052407