ICS1523 Datasheet, PDF (19/21 Pages) Integrated Circuit Systems – Video Clock Synthesizer with I2C Programmable Delay

ICS1523
Video Clock Synthesizer with I²C Programmable Delay
Parameter
Symbol
Min.
Max.
Analog Input (HSYNC)
Input High Voltage
V_IH
1.7
5.5
Input Low Voltage
V_IL
VSS - 0.3
1.1
Digital Inputs (SDA, SCL, EXTFB, OSC, I²CADDR)
Input High Voltage
Input Low Voltage
Input Hysteresis
POR Threshold
V_IH
2
5.5
V_IL
VSS - 0.3
0.8
-
0.2
0.6
-
VSS
1.8
SDA Digital Output
SDA Output Low Voltage
V_OL
0.4
SDA Output High Voltage
V_OH
6.0
PECL Outputs (CLK+, CLK-, CLK/2+, CLK/2-)
Output High Voltage
V_OH
-
Maximum Output Frequency
F_P MAX
-
Output Low Voltage *
V_OL
1.0
VDD
250
-
Duty Cycle
P_DC
45
55
Transition Time - Rise
T_PR
-
1.0
Transition Time - Fall
T_PF
-
1.2
SSTL_3 Outputs (CLK, CLK/2, FUNC, LOCK/REF)
Output Resistance
R_O
-
80
Maximum Output Frequency
F_s MAX
-
150
Duty Cycle
S_DC
45
55
Clock and FUNC
Transition Time - Rise
T_CR
-
1.6
Clock and FUNC
Transition Time - Fall
T_CF
-
1.0
LOCK/REF Transition Time -
T_LR
Rise
-
3.0
LOCK/REF Transition Time - Fall
T_LF
-
2.0
Units
V
V
Notes
V
V
V
V
Voltage that resets
register values
V
IOUT = 3ma
V
Determined by
external Rset
resistor
V
MHz
V
%
ns
ns
IOUT=0
VDDD = 3.3 V
IOUT =
Programmed Value
1
2
2
2
Ω
MHz
%
ns
ns
ns
ns
1 V < V_O < 2 V
VDDD = 3.3 V
3
3
3
3
3
Note 1- V_OL must not fall below the level given so that the correct value for IOUT can be maintained.
Note 2- Measured at 135MHz, 3.6 VDC, 0^oC, 20 pF, with 75 Ω Termination.
Note 3- Measured at 135MHz, 3.6 VDC, 0^oC, 20 pF, Unterminated.
MDS ICS1523 Z
19
Integrated Device Technology, Inc. Tech Support: www.idt.com/go/clockhelp
Revision 052407