ICS1523 Datasheet, PDF (14/21 Pages) Integrated Circuit Systems – Video Clock Synthesizer with I2C Programmable Delay

ICS1523
Video Clock Synthesizer with I²C Programmable Delay
Section 12 Timing Diagrams
Figure 12-1 DPA Operation
HSYNC
Fixed delay −See Figure 12-2 and Figure 12-3
DPA Offset when
DPA_OS [5-0] = 0
DPA Offset when
DPA_OS [5-0] = 1
One full speed clock period
1 unit of DPA delay
2 units of DPA delay
DPA Offset when
DPA_OS [5-0] = 2
.
.
.
DPA Offset when
DPA_OS [5-0] = Max
Maximum units of DPA delay
1 unit of DPA delay
DPA Offset = CLK Period * (# of DPA Elements Selected [0x4:4~0]
(# of DPA Elements Available)[0x5:1-0]
Table 12-1 DPA Offset Ranges
Register 5
Total # of DPA
1~0
Elements
00
16
0x4:5-0
Maximum
Selected #
of DPA
Elements
0F
DPA Clock Range in MHz
Min
Max
48
160
01
32
1F
24
80
11
64
3F
12
40
Using the DPA above 160 MHz is not recommended. Set DPA_OS = 0 for speeds in excess of 160 MHz to bypass
the DPA. The DPA Resolution Select register (0x5:0~1) is double-buffered. Working registers are loaded only after
a DPA Software reset (0x8=xA)
MDS ICS1523 Z
14
Integrated Device Technology, Inc. Tech Support: www.idt.com/go/clockhelp
Revision 052407