7132SA100J Datasheet, PDF (9/16 Pages) Integrated Device Technology – HIGH SPEED 2K x 8 DUAL PORT STATIC RAM

IDT7132SA/LA and IDT 7142SA/LA
High Speed 2K x 8 Dual Port Static RAM
Military, Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature Supply Voltage Range^(5,6)
7132X20⁽²⁾
7142X20⁽²⁾
Com'l Only
7132X25⁽²⁾
7142X25⁽²⁾
Com'l, Ind
& Military
Symbol
Parameter
Min. Max. Min. Max.
WRITE CYCLE
tWC
Write Cycle Time⁽³⁾
20
____
25
____
tEW
Chip Enable to End-of-Write
15
____
20
____
tAW
Address Valid to End-of-Write
15
____
20
____
tAS
Address Set-up Time
0
____
0
____
tWP
Write Pulse Width⁽⁴⁾
15
____
15
____
tWR
Write Recovery Time
0
____
0
____
tDW
Data Valid to End-of-Write
10
____
12
____
tHZ
Output High-Z Time⁽¹⁾
____
10
____
10
tDH
Data Hold Time
0
____
0
____
tWZ
Write Enable to Output in High-Z⁽¹⁾
____
10
____
10
tOW
Output Active from End-of-Write⁽¹⁾
0
____
0
____
Symbol
Parameter
7132X55
7142X55
Com'l &
Military
Min. Max.
7132X35
7142X35
Com'l &
Military
Min. Max. Unit
35
____
30
____
30
____
0
____
25
____
0
____
15
____
____
15
0
____
____
15
0
____
7132X100
7142X100
Com'l &
Military
Min. Max.
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2692 tbl 09
Unit
WRITE CYCLE
tWC
Write Cycle Time⁽³⁾
55
____
100
____
ns
tEW
Chip Enable to End-of-Write
40
____
90
____
ns
tAW
Address Valid to End-of-Write
40
____
90
____
ns
tAS
Address Set-up Time
0
____
0
____
ns
tWP
Write Pulse Width⁽⁴⁾
30
____
55
____
ns
tWR
Write Recovery Time
0
____
0
____
ns
tDW
Data Valid to End-of-Write
20
____
40
____
ns
tHZ
Output High-Z Time⁽¹⁾
____
25
____
40
ns
tDH
Data Hold Time
0
____
0
____
ns
tWZ
Write Enable to Output in High-Z⁽¹⁾
____
30
____
40
ns
tOW
Output Active from End-of-Write⁽¹⁾
0
____
0
____
ns
NOTES:
2692 tbl 10
1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2). This parameter is guaranteed by device characterization
but is not production tested.
2. PLCC package only.
3. For Master/Slave combination, tWC = tBAA + tWP, since R/W = VIL must occur after tBAA.
4. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off data to be placed on the
bus for the required tDW. If OE is High during a R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP.
5. 'X' in part numbers indicates power rating (SA or LA).
6. Industrial temperature: for specific speeds, packages and powers contact your sales office.
6.942