7132SA100J Datasheet, PDF (13/16 Pages) Integrated Device Technology – HIGH SPEED 2K x 8 DUAL PORT STATIC RAM

IDT7132SA/LA and IDT 7142SA/LA
High Speed 2K x 8 Dual Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Timing Waveform of BUSY Arbitration Controlled by CE Timing⁽¹⁾
ADDR
"A" and "B"
ADDRESSES MATCH
CE"B"
CE"A"
BUSY"A"
tAPS⁽²⁾
tBAC
tBDC
Timing Waveform of BUSY Arbitration Controlled
by Address Match Timing⁽¹⁾
ADDR"A"
ADDR"B"
tAPS⁽²⁾
tRC or tWC
ADDRESSES MATCH
ADDRESSES DO NOT MATCH
BUSY"B"
tBAA
tBDA
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either left or right port. Port “B” is the opposite from port “A”.
2. If tAPS is not satisified, the BUSY will be asserted on one side or the other, but there is no guarantee on which side BUSY will be asserted (7132 only).
2692 drw 13
2692 drw 14
Truth Tables
Table I. Non-Contention Read/Write Control⁽⁴⁾
Left or Right Port⁽¹⁾
R/W CE OE
D0-7
Function
X
H
X
Z
Port Disabled and in Power-Down Mode, ISB2 or ISB4
X
H
X
Z
CER = CEL = VIH, Power-Down Mode, ISB1 or ISB3
L
L
X
DATAIN Data on Port Written into Memory⁽²⁾
H
L
L
DATAOUT Data in Memory Output on Port⁽³⁾
X
L
H
Z
High Impedance Outputs
NOTES:
1. A0L - A10L ≠ A0R - A10R
2. If BUSY = L, data is not written.
3. If BUSY = L, data may not be valid, see tWDD and tDDD timing.
4. 'H' = VIH, 'L' = VIL, 'X' = DON’T CARE, 'Z' = HIGH IMPEDANCE
61.432
2692 tbl 12