7132SA100J Datasheet, PDF (8/16 Pages) Integrated Device Technology – HIGH SPEED 2K x 8 DUAL PORT STATIC RAM

IDT7132SA/LA and IDT 7142SA/LA
High Speed 2K x 8 Dual Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Timing Waveform of Read Cycle No. 1, Either Side⁽¹⁾
ADDRESS
DATAOUT
BUSYOUT
tAA
tOH
PREVIOUS DATA VALID
tRC
tOH
DATA VALID
tBDDH^(2,3)
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Timing Waveform of Read Cycle No. 2, Either Side⁽¹⁾
CE
OE
DATAOUT
ICC
CURRENT
ISS
tACE
tAOE⁽³⁾
tLZ⁽⁴⁾
tLZ⁽⁴⁾
tPU
50%
tHZ⁽⁵⁾
tHZ⁽⁵⁾
VALID DATA
tPD⁽³⁾
50%
2692 drw 08
NOTES:
1. R/W = VIH, CE = VIL, and is OE = VIL. Address is valid prior to the coincidental with CE transition LOW.
2. tBDD delay is required only in the case where the opposite port is completing a write operation to the same address location. For simultaneous read operations, BUSY has
no relationship to valid output data.
3. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA, and tBDD.
4. Timing depends on which signal is asserted last, OE or CE.
5. Timing depends on which signal is de-asserted first, OE or CE.
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