7132SA100J Datasheet, PDF (11/16 Pages) Integrated Device Technology – HIGH SPEED 2K x 8 DUAL PORT STATIC RAM

IDT7132SA/LA and IDT 7142SA/LA
High Speed 2K x 8 Dual Port Static RAM
Military, Industrial and Commercial Temperature Ranges
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range^(7,8)
7132X20⁽¹⁾
7142X20⁽¹⁾
Com'l Only
7132X25⁽²⁾
7142X25⁽²⁾
Com'l, Ind
& Military
7132X35
7142X35
Com'l &
Military
Symbol
Parameter
Min. Max. Min. Max. Min. Max. Unit
BUSY Timing (For Master IDT7132 Only)
tBAA
BUSY Access Time from Address
____
20
____
20
____
20
ns
tBDA
BUSY Disable Time from Address
____
20
____
20
____
20
ns
tBAC
BUSY Access Time from Chip Enable
____
20
____
20
____
20
ns
tBDC
BUSY Disable Time from Chip Enable
____
20
____
20
____
20
ns
tWDD
Write Pulse to Data Delay⁽²⁾
____
50
____
50
____
60
ns
tWH
Write Hold After BUSY⁽⁶⁾
12
____
15
____
20
____
ns
tDDD
Write Data Valid to Read Data Delay⁽²⁾
____
35
____
35
____
35
ns
tAPS
Arbitration Priority Set-up Time⁽³⁾
5
____
5
____
5
____
ns
tBDD
BUSY Disable to Valid Data⁽⁴⁾
____
25
____
35
____
35
ns
BUSY Timing (For Slave IDT7142 Only)
tWB
Write to BUSY Input⁽⁵⁾
0
____
0
____
0
____
ns
tWH
Write Hold After BUSY⁽⁶⁾
12
____
15
____
20
____
ns
tWDD
Write Pulse to Data Delay⁽²⁾
____
40
____
50
____
60
ns
tDDD
Write Data Valid to Read Data Delay⁽²⁾
____
30
____
35
____
35
ns
7132X55
7142X55
Com'l &
Military
7132X100
7142X100
Com'l &
Military
2692 tbl 11a
Symbol
Parameter
Min. Max. Min. Max. Unit
BUSY Timing (For Master IDT7132 Only)
tBAA
BUSY Access Time from Address
____
30
____
50
ns
tBDA
BUSY Disable Time from Address
____
30
____
50
ns
tBAC
BUSY Access Time from Chip Enable
____
30
____
50
ns
tBDC
BUSY Disable Time from Chip Enable
____
30
____
50
ns
tWDD
Write Pulse to Data Delay⁽²⁾
____
80
____
120
ns
tWH
Write Hold After BUSY⁽⁶⁾
20
____
20
____
ns
tDDD
Write Data Valid to Read Data Delay⁽²⁾
____
55
____
100
ns
tAPS
Arbitration Priority Set-up Time⁽³⁾
5
____
5
____
ns
tBDD
BUSY Disable to Valid Data⁽⁴⁾
____
50
____
65
ns
BUSY Timing (For Slave IDT7142 Only)
tWB
Write to BUSY Input⁽⁵⁾
0
____
0
____
ns
tWH
Write Hold After BUSY⁽⁶⁾
20
____
20
____
ns
tWDD
Write Pulse to Data Delay⁽²⁾
____
80
____
120
ns
tDDD
Write Data Valid to Read Data Delay⁽²⁾
____
55
____
100
ns
NOTES:
1. PLCC package only.
2. Port-to-port delay through RAM cells from the writing port to the reading port, refer to “Timing Waveform of Write with Port -to-Port Read and BUSY.”
3. To ensure that the earlier of the two ports wins.
4. tBDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual) or tDDD – tDW (actual).
5. To ensure that a write cycle is inhibited on port "B" during contention on port "A".
6. To ensure that a write cycle is completed on port "B" after contention on port "A".
7. 'X' in part numbers indicates power rating (SA or LA).
8. Industrial temperature: for specific speeds, packages and powers contact your sales office.
2692 tbl 11b
61.412