7132SA100J Datasheet, PDF (10/16 Pages) Integrated Device Technology – HIGH SPEED 2K x 8 DUAL PORT STATIC RAM

IDT7132SA/LA and IDT 7142SA/LA
High Speed 2K x 8 Dual Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Timing Waveform of Write Cycle No. 1, (R/W Controlled Timing)^(1,5,8)
ADDRESS
OE
CE
R/W
DATA OUT
DATA IN
tWC
tAS⁽⁶⁾
(4)
tAW
tWP⁽²⁾
tWZ⁽⁷⁾
tDW
tHZ⁽⁷⁾
tWR⁽³⁾
tOW
tDH
tHZ⁽⁷⁾
(4)
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Timing Waveform of Write Cycle No. 2, (CE Controlled Timing)^(1,5)
ADDRESS
CE
R/W
DATA IN
tAS⁽⁶⁾
tWC
tAW
tEW⁽²⁾
tDW
tWR⁽³⁾
tDH
NOTES:
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1. R/W or CE must be HIGH during all address transitions.
2. A write occurs during the overlap (tEW or tWP) of CE = VIL and R/W = VIL.
3. tWR is measured from the earlier of CE or R/W going HIGH to the end of the write cycle.
4. During this period, the l/O pins are in the output state and input signals must not be applied.
5. If the CE LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal (CE or R/W) is asserted last.
7. This parameter is determined be device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load
(Figure 2).
8. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off data to be placed on the
bus for the required tDW. If OE is HIGH during a R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tWP.
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