7132SA100J Datasheet, PDF (14/16 Pages) Integrated Device Technology – HIGH SPEED 2K x 8 DUAL PORT STATIC RAM

IDT7132SA/LA and IDT 7142SA/LA
High Speed 2K x 8 Dual Port Static RAM
Table II — Address BUSY
Arbitration
Inputs
Outputs
CEL CER
AOL-A10L
AOR-A10R
BUSYL⁽¹⁾ BUSYR⁽¹⁾
Function
X X NO MATCH
H
H
Normal
HX
MATCH
H
H
Normal
XH
MATCH
H
H
Normal
L
L
MATCH
(2)
(2)
Write Inhibit⁽³⁾
NOTES:
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1. Pins BUSYL and BUSYR are both outputs for IDT7132 (master). Both are inputs for
IDT7142 (slave). BUSYX outputs on the IDT7132 are open drain, not push-pull
outputs. On slaves the BUSYX input internally inhibits writes.
2. 'L' if the inputs to the opposite port were stable prior to the address and enable inputs
of this port. 'H' if the inputs to the opposite port became stable after the address and
enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR = LOW will
result. BUSYL and BUSYR outputs can not be LOW simultaneously.
3. Writes to the left port are internally ignored when BUSYL outputs are driving LOW
regardless of actual logic level on the pin. Writes to the right port are internally
ignored when BUSYR outputs are driving LOW regardless of actual logic level on
the pin.
Military, Industrial and Commercial Temperature Ranges
The BUSY outputs on the IDT7132 RAM master are open drain type
outputs and require open drain resistors to operate. If these RAMs are
being expanded in depth, then the BUSY indication for the resulting array
does not require the use of an external AND gate.
Width Expansion with Busy Logic
Master/Slave Arrays
When expanding an SRAM array in width while using BUSY logic,
one master part is used to decide which side of the SRAM array will
receive a BUSY indication, and to output that indication. Any number
of slaves to be addressed in the same address range as the master,
use the BUSY signal as a write inhibit signal. Thus on the IDT7132/
IDT7142 SRAMs the BUSY pin is an output if the part is Master (IDT7132),
and the BUSY pin is an input if the part is a Slave (IDT7142) as shown
in Figure 3.
5V
270Ω
MASTER
Dual Port
SRAM
BUSYL
CE
BUSYR
SLAVE
Dual Port
SRAM
BUSYL
CE
BUSYR
5V
270Ω
Functional Description
The IDT7132/IDT7142 provides two ports with separate control,
address and I/O pins that permit independent access for reads or
writes to any location in memory. The IDT7132/IDT7142 has an
automatic power down feature controlled by CE. The CE controls on-
chip power down circuitry that permits the respective port to go into a
standby mode when not selected (CE = VIH). When a port is enabled,
access to the entire memory array is permitted.
Busy Logic
Busy Logic provides a hardware indication that both ports of the
RAM have accessed the same location at the same time. It also allows
one of the two accesses to proceed and signals the other side that the
RAM is “Busy”. The BUSY pin can then be used to stall the access until
the operation on the other side is completed. If a write operation has
been attempted from the side that receives a busy indication, the write
signal is gated internally to prevent the write from proceeding.
The use of BUSY Logic is not required or desirable for all applica-
tions. In some cases it may be useful to logically OR the BUSY outputs
together and use any BUSY indication as an interrupt source to flag the
event of an illegal or illogical operation.
BUSYL
MASTER
Dual Port
SRAM
BUSYL
CE
BUSYR
SLAVE
Dual Port
SRAM
BUSYL
CE
BUSYR
BUSYR
2692 drw 15
Figure 4. Busy and chip enable routing for both width and depth
expansion with IDT7132 (Master) and (Slave) IDT7142 SRAMs.
If two or more master parts were used when expanding in width, a
split decision could result with one master indicating BUSY on one side
of the array and another master indicating BUSY on one other side of
the array. This would inhibit the write operations from one port for part
of a word and inhibit the write operations from the other port for the
other part of the word.
The BUSY arbitration, on a Master, is based on the chip enable and
address signals only. It ignores whether an access is a read or write.
In a master/slave array, both address and chip enable must be valid
long enough for a BUSY flag to be output from the master before the
actual write pulse can be initiated with either the R/W signal or the byte
enables. Failure to observe this timing can result in a glitched internal
write inhibit signal and corrupted data in the slave.
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