ICS9FG1200D-1 Datasheet, PDF (8/23 Pages) Integrated Device Technology – Frequency Gearing Clock for CPU, PCIe Gen1, Gen2

ICS9FG1200D-1
Frequency Gearing Clock for CPU, PCIe Gen1, Gen2 & FBD
Electrical Characteristics - DIF 0.7V Current Mode Differential Pair
T_A = 0 - 70°C; V_DD = 3.3 V +/-5%; C_L =2pF, R_S=33.2Ω, R_P=49.9Ω, Ι_REF = 475Ω
PARAMETER
SYMBOL
CONDITIONS
MIN TYP
Current Source Output
Impedance
Voltage High
Voltage Low
Max Voltage
Min Voltage
Crossing Voltage (abs)
Crossing Voltage (var)
Long Accuracy
Average period
Absolute min period
Rise Time
Fall Time
Rise Time Variation
Fall Time Variation
Duty Cycle
Jitter, Cycle to cycle
Zo¹
V_O = V_x
VHigh
VLow
Vovs
Vuds
Vcross(abs)
d-Vcross
ppm
Tperiod
T_absmin
t_r
t_f
d-t_r
d-t_f
d_t3
t_JCYC-CYC
Statistical measurement on
single ended signal using
oscilloscope math function.
Measurement on single ended
signal using absolute value.
Variation of crossing over all
edges
see Tperiod min-max values
400MHz nominal
400MHz spread
333.33MHz nominal
333.33MHz spread
266.66MHz nominal
266.66MHz spread
200MHz nominal
200MHz spread
166.66MHz nominal
166.66MHz spread
133.33MHz nominal
133.33MHz spread
100.00MHz nominal
100.00MHz spread
400MHz nominal/spread
333.33MHz nominal/spread
266.66MHz nominal/spread
200MHz nominal/spread
166.66MHz nominal/spread
133.33MHz nominal/spread
100.00MHz nominal/spread
V_OL = 0.175V, V_OH = 0.525V
V_OH = 0.525V V_OL = 0.175V
Measurement from differential
wavefrom
PLL mode,
from differential wavefrom
t_JBYP
Bypass mode as additive jitter
3000
660
-150
-300
250
-300
2.4993
2.4993
2.9991
2.9991
3.7489
3.7489
4.9985
4.9985
5.9982
5.9982
7.4978
7.4978
9.9970
9.9970
2.4143
2.9141
3.6639
4.8735
5.8732
7.3728
9.8720
175
175
45
MAX
850
150
1150
550
140
300
2.5008
2.5133
3.0009
3.016
3.7511
3.77
5.0015
5.0266
6.0018
6.0320
7.5023
7.5400
10.0030
10.0533
700
700
125
125
55
50
50
UNITS NOTES
Ω
1
1,3
mV
1,3
mV
1
1
mV
1
mV
1
ppm 1,2
ns
2
ns
2
ns
2
ns
2
ns
2
ns
2
ns
2
ns
2
ns
2
ns
2
ns
2
ns
2
ns
2
ns
2
ns
1,2
ns
1,2
ns
1,2
ns
1,2
ns
1,2
ns
1,2
ns
1,2
ps
1
ps
1
ps
1
ps
1
%
1
ps 1,4,5
ps
1,4
Notes:
1.Guaranteed by design and characterization, not 100% tested in production.
2. All Long Term Accuracy and Clock Period specifications are guaranteed assuming that the input frequency meets CK410B+ accuracy requirements
3.IREF = VDD/(3xRR). For RR = 475Ω (1%), IREF = 2.32mA. IOH = 6 x IREF and VOH = 0.7V @ ZO=50Ω.
4. Measured into fixed 2 pF load cap. Input to output skew is measured at the first output edge following the corresponding input.
5. Measured from differential cross-point to differential cross-point
6. All Bypass Mode Input-to-Output specs refer to the timing between an input edge and the specific output edge created by it.
IDT^® Frequency Gearing Clock for CPU, PCIe Gen1, Gen2 & FBD
1138C 02/08/10
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