ICS9FG1200D-1 Datasheet, PDF (2/23 Pages) Integrated Device Technology – Frequency Gearing Clock for CPU, PCIe Gen1, Gen2

ICS9FG1200D-1
Frequency Gearing Clock for CPU, PCIe Gen1, Gen2 & FBD
Pin Configuration
Power Groups
Pin Number
VDD
GND
56
11,22,38,50
55
12,23,37,49
HIGH_BW# 1
CLK_IN 2
CLK_IN# 3
SMB_A0 4
OE0# 5
DIF_0 6
DIF_0# 7
OE1# 8
DIF_1 9
DIF_1# 10
VDD 11
GND 12
DIF_2 13
DIF_2# 14
OE2# 15
DIF_3 16
DIF_3# 17
OE3# 18
DIF_4 19
DIF_4# 20
OE4# 21
VDD 22
GND 23
DIF_5 24
DIF_5# 25
OE5# 26
SMB_A1 27
SMBDAT 28
56 VDDA
55 GNDA
54 IREF
53 OE10_11#
52 DIF_11
51 DIF_11#
50 VDD
49 GND
48 DIF_10
47 DIF_10#
46 FS_A_410
45 VTT_PWRGD#/PD
44 OE9#
43 DIF_9
42 DIF_9#
41 OE8#
40 DIF_8
39 DIF_8#
38 VDD
37 GND
36 DIF_7
35 DIF_7#
34 OE7#
33 DIF_6
32 DIF_6#
31 OE6#
30 SMB_A2_PLLBYP#
29 SMBCLK
56-pin SSOP & TSSOP
Description
Main PLL, Analog
DIF clocks
Functionality at Power Up (PLL Mode)
FS_A_410¹
CLK_IN (CPU FSB)
MHz
DIF_(11:0)
MHz
1
100 <= CLK_IN < 200
CLK_IN
0
200<= CLK_IN <= 400
CLK_IN
1. FS_A_410 is a low-threshold input. Please see the V_{IL_FS} and V_{IH_FS}
specifications in the Input/Supply/Common Output Parameters Table for correct values.
IDT^® Frequency Gearing Clock for CPU, PCIe Gen1, Gen2 & FBD
2
1138C 02/08/10