ICS9FG1200D-1 Datasheet, PDF (12/23 Pages) Integrated Device Technology – Frequency Gearing Clock for CPU, PCIe Gen1, Gen2

ICS9FG1200D-1
Frequency Gearing Clock for CPU, PCIe Gen1, Gen2 & FBD
General SMBus serial interface information for the 9FG1200D-1
How to Write:
• Controller (host) sends a start bit.
• Controller (host) sends the write address D0 _(h)
• ICS clock will acknowledge
• Controller (host) sends the begining byte location = N
• ICS clock will acknowledge
• Controller (host) sends the data byte count = X
• ICS clock will acknowledge
• Controller (host) starts sending Byte N through
Byte N + X -1
• ICS clock will acknowledge each byte one at a time
• Controller (host) sends a Stop bit
How to Read:
• Controller (host) will send start bit.
• Controller (host) sends the write address D0 _(h)
• ICS clock will acknowledge
• Controller (host) sends the begining byte
location = N
• ICS clock will acknowledge
• Controller (host) will send a separate start bit.
• Controller (host) sends the read address D1 _(h)
• ICS clock will acknowledge
• ICS clock will send the data byte count = X
• ICS clock sends Byte N + X -1
• ICS clock sends Byte 0 through byte X (if X_(h)
was written to byte 8).
• Controller (host) will need to acknowledge each byte
• Controllor (host) will send a not acknowledge bit
• Controller (host) will send a stop bit
Index Block Write Operation
Controller (Host)
T
starT bit
ICS (Slave/Receiver)
Slave Address D0_(h)*
WR
WRite
ACK
Beginning Byte = N
ACK
Data Byte Count = X
ACK
Beginning Byte N
ACK
Byte N + X - 1
P
stoP bit
ACK
Index Block Read Operation
Controller (Host)
ICS (Slave/Receiver)
T
starT bit
Slave Address D0_(h)*
WR
WRite
ACK
Beginning Byte = N
ACK
RT
Repeat starT
Slave Address D1_(h)*
RD
ReaD
ACK
ACK
ACK
Data Byte Count = X
Beginning Byte N
N Not acknowledge
P
stoP bit
Byte N + X - 1
* Note: See SMBus Address Mapping (page 10), for programming SMBus Read/Write Address
IDT^® Frequency Gearing Clock for CPU, PCIe Gen1, Gen2 & FBD
12
1138C 02/08/10