ICS9FG1200D-1 Datasheet, PDF (1/23 Pages) Integrated Device Technology – Frequency Gearing Clock for CPU, PCIe Gen1, Gen2

DATASHEET
Frequency Gearing Clock for CPU, PCIe Gen1, Gen2
& FBD
ICS9FG1200D-1
Description
ICS9FG1200D-1 follows the Intel DB1200GS Differential Buffer
Specification. This buffer provides 12 output clocks for CPU Host
Bus, PCIe Gen2, or Fully Buffered DIMM applications.The outputs
are configured with two groups. Both groups (DIF 9:0) and (DIF
11:10) can be equal to or have a gear ratio to the input clock. A
differential CPU clock from a CK410B+ main clock generator,
such as the ICS932S421, drives the ICS9FG1200D-1. The
ICS9FG1200D-1 can provide outputs up to 400MHz.
Key Specifications
• DIF output cycle-to-cycle jitter < 50ps
• DIF output-to-output skew < 100ps across all outputs in 1:1
mode
• 56-pin SSOP/TSSOP package
• RoHS compliant packaging
Features/Benefits
• Drives 2 channels of 4 FBDIMMs (total of 8 FBDIMMs)
• Power up default is all outputs in 1:1 mode
• DIF_(9:0) can be “gear-shifted” from the input CPU Host
Clock
• DIF_(11:10) can be “gear-shifted” from the input CPU
Host Clock
• Spread spectrum compatible
• Supports output clock frequencies up to 400 MHz
• 8 Selectable SMBus addresses
• SMBus address determines PLL or Bypass mode
Functional Block Diagram
OE#
10
OE(9:0)#
SPREAD
COMPATIBLE
1:1 PLL
CLK_IN
CLK_IN#
SPREAD
COMPATIBLE
GEARING PLL
HIGH_BW#
FS_A_410
VTT_PWRGD#/PD
SMB_A0
SMB_A1
SMB_A2_PLLBYP#
SMBDAT
SMBCLK
CONTROL
LOGIC
STOP
2
LOGIC
DIF(11:10)
STOP ¹⁰
LOGIC
DIF(9:0)
IREF
IDT^® Frequency Gearing Clock for CPU, PCIe Gen1, Gen2 & FBD
1
1138C 02/08/10